Home » CSE VIVA Questions » 20 TOP MOST Digital Logic Design VIVA Questions and Answers – CSE 20 TOP MOST Digital Logic Design VIVA Questions and Answers – CSE Posted on August 19, 2018March 14, 2017 by engineerLeave a comment Digital Logic Design VIVA Questions and Answers :- 1) Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this? 2) What is skew, what are problems associated with it and how to minimize it? 3) What is slack? 4) What is glitch? What causes it (explain with waveform)? How to overcome it? 5) Given only two xor gates one must function as buffer and another as inverter? 6) What is difference between latch and flipflop? 7) Build a 4:1 mux using only 2:1 mux? 8) Difference between heap and stack? Digital Logic Design VIVA Questions and Answers :- 9) Difference between mealy and moore state machine? 10) Difference between onehot and binary encoding? 11) How to achieve 180 degree exact phase shift? 12) What is significance of ras and cas in SDRAM? 13) Tell some of applications of buffer? 14) Implement an AND gate using mux? 15) What will happen if contents of register are shifter left, right? 16)Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?