VLSI Interview Questions and Answers for Experienced people focuses on “Storage Elements-2”.
1. Overhead bits are used for sensing.
A. true
B. false
Answer: A
Clarification: Overhead bits are used for sensing. Some amount of over head bits are used in one transistor dynamic memory cell.
2. Reading a cell is a _______ operation.
A. constructive
B. destructive
C. semi constructive
D. semi destructive
Answer: B
Clarification: Reading a cell is a destructive operation and the stored bit must be rewritten everytime it is read.
3. RAM is a _____ cell.
A. dynamic
B. partially dynamic
C. static
D. pseudo static
Answer: D
Clarification: RAM is a pseudo static cell. It stores data indefinitely and refreshing is not necessary.
4. Pseudo static RAM cell is built using
A. one inverter
B. two inverters
C. three inverters
D. four inverters
Answer: B
Clarification: Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.
5. Cells must be non stackable in RAM storage cell.
A. true
B. false
Answer: B
Clarification: Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when layout is made.
6. Which cell is non volatile?
A. one transistor dynamic cell
B. two transistor dymanic cell
C. four transistor dynamic cell
D. pseudo static RAM cell
Answer: D
Clarification: Pseudo static RAM cell is a non volatile cell. It is used for long time storage. Non volatile memory is also called as long term memory.
7. In RAM arrays, the transistor is of
A. minimum size
B. maximum size
C. of any size
D. size doesn’t play a role
Answer: A
Clarification: In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.
8. Which implementation is slower?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: B
Clarification: NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.
9. FOR nMOS which implementation is not suitable?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: A
Clarification: In nMOS, NAND gate implementation is impractical because of the large number of gate requiring three or more inputs.
10. Realization of JK flipflop is based on
A. n-pass transistor
B. p-pass transistor
C. CMOS
D. BiCMOS
Answer: A
Clarification: The realization of JK flip flop is based on n-pass transistor and on inverters only.
11. Static RAM uses ____________ transistors.
A. four
B. five
C. six
D. seven
Answer: C
Clarification: Static RAM uses six transistors. In this RAM cell, read and write operations use the same port.
f VLSI for Interviews,