Digital Electronics/Circuits Multiple Choice Questions on “Triggering of Flip Flops”.
1. The characteristic equation of J-K flip-flop is ______________
A. Q(n+1)=JQ(n)+K’Q(n)
B. Q(n+1)=J’Q(n)+KQ'(n)
C. Q(n+1)=JQ'(n)+KQ(n)
D. Q(n+1)=JQ'(n)+K’Q(n)
Answer: D
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).
2. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer: C
Clarification: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.
3. In J-K flip-flop, the function K=J is used to realize _____________
A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer: C
Clarification: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.
4. The only difference between a combinational circuit and a flip-flop is that _____________
A. The flip-flop requires previous state
B. The flip-flop requires next state
C. The flip-flop requires a clock pulse
D. The flip-flop depends on the past as well as present states
Answer: C
Clarification: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as well as present states. Whereas, in case of combinational circuits, they only depend on the present state.
5. How many stable states combinational circuits have?
A. 3
B. 4
C. 2
D. 5
Answer: C
Clarification: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional state known as Forbidden State.
6. The flip-flop is only activated by _____________
A. Positive edge trigger
B. Negative edge trigger
C. Either positive or Negative edge trigger
D. Sinusoidal trigger
Answer: C
Clarification: Flip flops can be activated with either a positive or negative edge trigger.
7. The S-R latch composed of NAND gates is called an active low circuit because _____________
A. It is only activated by a positive level trigger
B. It is only activated by a negative level trigger
C. It is only activated by either a positive or negative level trigger
D. It is only activated by sinusoidal trigger
Answer: B
Clarification: Active low indicates that only an input value of 0 sets or resets the circuit.
8. Both the J-K & the T flip-flop are derived from the basic _____________
A. S-R flip-flop
B. S-R latch
C. D latch
D. D flip-flop
Answer: B
Clarification: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A latch is similar to a flip-flop, only without a clock input.
9. The flip-flops which has not any invalid states are _____________
A. S-R, J-K, D
B. S-R, J-K, T
C. J-K, D, S-R
D. J-K, D, T
Answer: D
Clarification: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or forbidden state where no output could be determined.
10. What does the triangle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Edge triggered
C. Both Level enabled & Edge triggered
D. Level triggered
Answer: B
Clarification: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.
11. What does the circle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: C
Clarification: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.
12. What does the direct line on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: D
Clarification: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.
13. What does the half circle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: D
Clarification: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.
14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer: D
Clarification: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.
15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
A. The clock pulse is LOW
B. The clock pulse is HIGH
C. The clock pulse transitions from LOW to HIGH
D. The clock pulse transitions from HIGH to LOW
Answer: C
Clarification: Edge triggered device will follow the input condition when there is a transition. It is said to be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be a negative edge triggered when a transition occurs from HIGH to LOW.