This set of VHDL Multiple Choice Questions & Answers (MCQs) on “IF Statement”.
1. What kind of statement is the IF statement?
a) Concurrent
b) Sequential
c) Assignment
d) Selected assignment
Answer: b
Clarification: IF statement is a sequential statement which appears inside a process, function or subprogram. This statement is used to execute some block of statements if a condition executed comes to be true.
2. Which of the following keyword is not associated with IF statement?
a) ELSE
b) THEN
c) ELSIF
d) WHEN
Answer: d
Clarification: The IF statement can use the keywords ELSIF, THEN and ELSE but not the keyword WHEN. IF statement is followed by a condition which is followed by the keyword THEN. After which to add more conditions one can use ELSIF and ELSE keywords.
3. Which of the following represents the correct order for keywords?
a) IF, THEN, ELSIF, THEN, ELSE
b) IF, ELSE, THEN, ELSIF, THEN
c) IF, ELSIF, THEN, ELSE, THEN
d) IF, THEN, ELSE, THEN, ELSIF
Answer: a
Clarification: In case of IF statement, the keyword IF is followed by the condition and then the keyword THEN. After this any other condition is entered by using ELSIF keyword and all the other exceptions are handled by using ELSE keyword. So, the correct order is shown in option a which is IF, THEN, ELSIF, THEN, ELSE.
4. What is the correct syntax for defining an IF statement?
a)
IF (condition) THEN statements; ELSIF (condition) THEN statements; ….; ELSE (condition) THEN statements; END IF;
b)
IF (condition) THEN statements; ELSIF (condition) THEN statements; ….; ELSE statements; END IF;
c)
IF (condition) THEN statements; ELSIF (condition) THEN statements; ….; ELSE (condition) statements; END IF-ELSE;
d)
IF (condition) THEN statements; ELSIF (condition) THEN statements; ….; ELSE statements; END IF-ELSE;
View Answer
Answer: b
Clarification: For a sequential IF statement, the condition is evaluated and if it is found to be true then the statements under IF are executed and after that the sequence of ELSIFs is used and finally an ELSE is used and it is ended by using END keyword followed by IF.
5. If the condition of IF statement is an expression, then what should be the type of the result of the expression?
a) Bit
b) Std_logic
c) Boolean
d) Integer
Answer: c
Clarification: It doesn’t matter what is the type of the expression, the result must be of Boolean type. It can have only two values which may be either TRUE or FALSE. If the result is true, THEN the statements under IF are executed otherwise ELSE is executed.
6. In the following lines, what should be the value of signal y, if a and b both are at logic high?
PROCESS (a, b) BEGIN IF( a XOR b <=’1’) y <= ‘1’; ELSIF (a AND b <= ‘0’) y <= a; ELSE y <= ‘0’; END IF; END PROCESS;
a) a
b) b
c) 0
d) 1
Answer: c
Clarification: At the time of synthesis, first the condition of IF statement is tested and it is found to be FALSE, so the statements under IF statements are skipped and the condition of ELSIF is tested. That condition again comes to be FALSE and hence the statement under else is executed. So, y is assigned 1.
7. It is possible to use nested IF in VHDL.
a) True
b) False
Answer: a
Clarification: Like other traditional languages, it is possible to use an IF statement inside another IF statement. In this case, when one IF statement is used inside another IF statement, this is called the nested IF statement. This allows to use more than one condition simultaneously.
8. Which of the following condition has topmost priority?
a) IF
b) ELSIF
c) ELSE
d) THEN
Answer: a
Clarification: IF has the topmost priority which means the remaining block will be executed only if the condition under IF gives FALSE. Otherwise, if it is true, then the block is shifted until END IF statement. After the IF condition, the next priority is ELSIF condition. ELSE is executed only if every preceding condition is FALSE.
9. What logic is described in the following logic?
PROCESS (a, b) IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN y <= ‘1’; ELSIF (a = ‘1’ AND b= ‘1’) THEN y <= ‘0’; ELSE y <= ‘0’; END IF
a) EXOR
b) EXNOR
c) AND
d) NOR
Answer: a
Clarification: Here, in the given code, the output is 1 if either a is 1 or b is 1. In the ELSIF, the condition is that the output will be zero if both the inputs are 1. So, both inputs can’t be high at the same time. Therefore, the logic described is exclusive OR logic.
10. One IF statement can have multiple ___________
a) IF
b) ELSIF
c) ELSE
d) CASE
Answer: b
Clarification: It is possible to have multiple ELSIF parts within one IF – END IF block. The IF statement can have multiple ELSIF parts but can have only one ELSE statement part. ELSE part will be executed after each of the ELSIF part is checked and found to be FALSE.
11. More than one sequential statement can exist between each statement part.
a) True
b) False
Answer: a
Clarification: Yes, It is not necessary that within a single IF or ELSIF, only one sequential statement is allowed. Multiple statements can be there between each statement part. Unlike, traditional languages it doesn’t need {} to write multiple statements.
12. If a user gets an error at the time of simulation which is “ the IF statement is illegal” what could be the reason?
a) Using IF statement in architecture body
b) Using IF statement without ELSE
c) Using multiple ELSE statements
d) Using concurrent assignment in the IF
Answer: a
Clarification: It is not allowed to use IF in the architecture body directly. IF statement is a sequential statement and hence can be used in a process, function or procedure. However, using IF statement without ELSE is not any error, doing this is possible. The only error is that it can’t be used in the concurrent.
13. In a clocked process, IF statement is used to __________
a) To run statements sequentially
b) To use concurrent assignment within process
c) To detect the clock signal
d) To implement sequential circuit
Answer: c
Clarification: A clocked process is the process which uses a clock signal to design the circuit. In such process one may need to detect the rising or falling edge of the clock. For this purpose, IF statement can be used to detect the occurrence of a clock.
14. What will be the output in the following code?
ARCHITECTURE my_logic OF my_design IS BEGIN a <= 1; b <= 1; PROCESS (a, b) BEGIN IF (a AND b = 1) THEN output <= a; ELSIF (a OR b = 1) THEN output <= b; ELSE output <= 0; END IF; END PROCESS; END my_logic;
a) 0
b) 1
c) b
d) a
Answer: d
Clarification: Since the condition under IF is true so the statements under IF will be executed and hence output will be assigned the value of signal a. Though the condition under ELSIF is also TRUE but IF has the highest priority so all the following ELSIFs will be ignored. This is the problem in IF statement.