Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “Register-Transistor Logic(RTL)”.

1. All input of NOR as low produces result as __________
A. Low
B. Mid
C. High
D. Floating
Answer: C
Clarification: All input of NOR as low produces the result as high, whereas, rest all conditions produce output as low.

2. In RTL NOR gate, the output is at logic 1 only when all the inputs are at __________
A. logic 0
B. logic 1
C. +10V
D. Floating
Answer: A
Clarification: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at logic 0 and in rest conditions of the input, the output is 0.

3. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the input network and _______ as switching devices.
A. Resistors, bipolar junction transistors (BJTs)
B. Bipolar junction transistors (BJTs), Resistors
C. Capacitors, resistors
D. Resistors, capacitors
Answer: A
Clarification: Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices.

4. RTL consists of a common emitter stage with a _______ connected between the base and the input voltage source.
A. collector
B. base resistor
C. capacitor
D. inductor
Answer: B
Clarification: RTL consist of a common emitter stage with a base resistor connected between the base and the input voltage source. The role of base resistor is to expand the negligible transistor input voltage range (about 0.7 V) to the logical “1” level (about 3.5 V) by converting the input voltage into a current. Thus, base resistor plays a major role in biasing of the transistor.

5. The role of the _______ is to convert the collector current into a voltage in RTL.
A. Collector resistor
B. Base resistor
C. Capacitor
D. Inductor
Answer: A
Clarification: The role of the collector resistor is to convert the collector current into a voltage; its resistance is chosen high enough to saturate the transistor and low enough to obtain low output resistance. Base Resistor is to provide the necessary biasing to the base of the transistor in order to activate it.

6. The limitations of the one transistor RTL NOR gate are overcome by __________
A. Two-transistor RTL implementation
B. Three-transistor RTL implementation
C. Multi-transistor RTL implementation
D. Four-transistor RTL implementation
Answer: C
Clarification: The limitations of the one transistor RTL NOR gate are overcome by the use of multi transistor RTL. It consists of a set of parallel connected transistor switches driven by the logic inputs.

7. The primary advantage of RTL technology was that __________
A. It results as low power dissipation
B. It uses a minimum number of resistors
C. It uses a minimum number of transistors
D. It operates swiftly
Answer: C
Clarification: The primary advantage of RTL technology was that it uses a minimum number of transistors. It consists of registers in large amount and it results in as high power dissipation. The resistors act as the input network and the transistors performs the switching operation.

8. The disadvantage of RTL is that __________
A. It uses a maximum number of resistors
B. It results in high power dissipation
C. High noise creation
D. It uses a minimum number of transistors
Answer: B
Clarification: The disadvantage of RTL is its high power dissipation when the transistor is switched on by current flowing in the collector and base resistor. This requires that more current be supplied to and heat be removed from RTL circuits. In contrast, TTL circuits with “totem-pole” output stage minimize both of these requirements.

9. TTL circuits with “totem-pole” output stage minimize __________
A. The power dissipation in RTL
B. The time consumption in RTL
C. The speed of transferring rate in RTL
D. Propagation delay in RTL
Answer: A
Clarification: TTL circuits with “totem-pole” output stage minimize the power dissipation and heating effect in RTL.

10. The minimum number of transistors can be used by 2 input AND gate is __________
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: The minimum number of transistors can be used by 2 input AND gate is 2 and maximum up to 3.

Digital Electronic/Circuits Test on “4-Bit Parallel Adder/Subtractor – 2”.

1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is ___________
A. The same as if the carry-in is tied LOW since the least significant carry-in is ignored
B. That carry-out will always be HIGH
C. A one will be added to the final result
D. The carry-out is ignored
Answer: C
Clarification: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be added to the final result as a result because carry-in gives output as 1.

2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which ___________
A. Determine sign and magnitude
B. Reduce propagation delay
C. Add a 1 to complemented inputs
D. Increase ripple delay
Answer: B
Clarification: A carry-lookahead adder (CLA. is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It reduces the propagation delay by making the hardware more complex. The ripple carry design is converted in such a way that carry over a group of bits of the adder becomes 2-level logic.

3. One way to make a four-bit adder to perform subtraction is by ___________
A. Inverting the output
B. Inverting the carry-in
C. Inverting the B inputs
D. Grounding the B inputs
Answer: C
Clarification: A adder is a digital circuit which adds bits along with a carry bit from a previous stage, thus producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and a carry at the input end. So, for subtraction to be performed, all the Bs terminal should be inverted.

4. What distinguishes the look-ahead-carry adder?
A. It is slower than the ripple-carry adder
B. It is easier to implement logically than a full adder
C. It is faster than a ripple-carry adder
D. It requires advance knowledge of the final answer
Answer: C
Clarification: It is faster than ripple carry adder as it reduces the propagation delay by converting the ripple carry in such a way that the carry over a group of bits of the adder becomes 2-level logic.

5. Carry lookahead logic uses the concepts of ___________
A. Inverting the inputs
B. Complementing the outputs
C. Generating and propagating carries
D. Ripple factor
Answer: C
Clarification: Look Ahead Carry Adder is a type of digital circuit which reduces the propagation delay. Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this.

6. What is one disadvantage of the ripple-carry adder?
A. The interconnections are more complex
B. More stages are required to a full adder
C. It is slow due to propagation time
D. All of the Mentioned
Answer: C
Clarification: The main disadvantage in using this type of adders is that the time delay increases as for each adder to add the carry should be generated in the previous adder, and for that to add the carry from the one before is required. However, this disadvantage is taken care of in Carry Look Ahead adder in which the ripple carry is converted in such a way that the carry over a group of bits of the adder becomes 2-level logic.

7. The carry propagation delay in 4-bit full-adder circuits ___________
A. Is cumulative for each stage and limits the speed at which arithmetic operations are performed
B. Is normally not a consideration because the delays are usually in the nanosecond range
C. Decreases in direct ratio to the total number of full-adder stages
D. Increases in direct ratio to the total number of full-adder stages but is not a factor in limiting the speed of arithmetic operations
Answer: A
Clarification: A full adder is a digital circuit with 3 inputs and two outputs SUM and CARRY. The carry propagation delay in 4-bit full-adder circuits is cumulative for each stage and limits the speed at which arithmetic operations are performed.

8. What is Manchester carry chain?
A. Is a chain of controlled inverter
B. Variation of a carry-lookahead adder
C. Variation of a full-adder
D. Variation of a ripple carry adder
Answer: B
Clarification: The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower the transistor count. However, the carry generating logic depends on the logic to generate the carries in the past.

9. The main disadvantage of Manchester carry chain is ___________
A. Ripple factor
B. Propagation delay
C. Capacitive load
D. Both propagation delay and capacitive load
Answer: D
Clarification: Propagation delay is the measure of time taken by the output to go to the next state when the input is altered. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead.

10. The summing outputs of a half or full-adder are designated by which Greek symbol?
A. Omega
B. Theta
C. Lambda
D. Sigma
Answer: D
Clarification: The summing outputs of a half or full-adder are designated by “sigma” which is a Greek symbol. This same symbol is used to signify the Minterms in case of an SOP expression.

11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
A. To decrease the cost
B. To make it smaller
C. To slow down the circuit
D. To speed up the circuit
Answer: D
Clarification: A Carry Look Ahead (CLA. Adder is a type of adder that reduce the propagation delay. A fast Carry Look Ahead Adder is more fast than a normal CLA. Since, it is easy to implement and can be implemented on any types of chip and have the capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit full-adder.

for various tests,

Digital Electronics/Circuits Multiple Choice Questions on “Universal Shift Registers”.

1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A. Ring shift
B. Clock
C. Johnson
D. Binary
Answer: A
Clarification: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. Thus, it generates equally spaced timing pulses.

2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________
A. 1101
B. 0111
C. 0001
D. 1110
Answer: B
Clarification: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011 and remained bit in register is 1. Therefore, 0111 is the required solution.
1011 | 1101
101 | 1110 -> 1^st clock pulse
10 | 1111 -> 2^nd clock pulse
1 | 0111 -> 3^rd clock pulse.

3. To operate correctly, starting a ring shift counter requires __________
A. Clearing all the flip-flops
B. Presetting one flip-flop and clearing all others
C. Clearing one flip-flop and presetting all others
D. Presetting all the flip-flops
Answer: B
Clarification: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. To operate correctly, starting a ring shift counter requires presetting one flip-flop and clearing all others so that it can shift to the next bit.

4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.
A. Right, one
B. Right, two
C. Left, one
D. Left, three
Answer: A
Clarification: If register shifts towards left then it shift by a bit to the left and if register shifts right then it shift to the right by one bit. Since, it receives parallel data, then by default, it will shift to right by one position.

5. How many clock pulses will be required to completely load serially a 5-bit shift register?
A. 2
B. 3
C. 4
D. 5
Answer: D
Clarification: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift register. So, for 5-bit shift register we would require of 5 clock pulses.

6. How is a strobe signal used when serially loading a shift register?
A. To turn the register on and off
B. To control the number of clocks
C. To determine which output Qs are used
D. To determine the FFs that will be used
Answer: B
Clarification: A strobe is used to validate the availability of data on the data line. It (an auxiliary signal used to help synchronize the real data in an electrical bus when the bus components have no common clock) signal is used to control the number of clocks during serially loading a shift register.

7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
A. 1.67 s
B. 26.67 s
C. 26.7 ms
D. 267 ms
Answer: B
Clarification: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.

8. What are the three output conditions of a three-state buffer?
A. HIGH, LOW, float
B. High-Z, 0, float
C. Negative, positive, 0
D. 1, Low-Z, float
Answer: A
Clarification: Three conditions of a three-state buffer are HIGH, LOW & float.

9. The primary purpose of a three-state buffer is usually ____________
A. To provide isolation between the input device and the data bus
B. To provide the sink or source current required by any device connected to its output without loading down the output device
C. Temporary data storage
D. To control data flow
Answer: A
Clarification: The primary purpose of a three-state buffer is usually to provide isolation between the input device or peripheral devices and the data bus. Three conditions of a three-state buffer are HIGH, LOW & float.

10. What is the difference between a ring shift counter and a Johnson shift counter?
A. There is no difference
B. A ring is faster
C. The feedback is reversed
D. The Johnson is faster
Answer: C
Clarification: A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Whereas, a Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage.

tough Digital Electronic/Circuits questions and answers on “Random Access Memory-3”.

1. Dynamic RAM is more preferable than static RAM, why?
A. DRAM is of the lowest cost, lowest density
B. DRAM is of the highest cost, reduced size
C. DRAM is of the lowest cost, highest density
D. DRAM is more flexible and lowest storage capacity
Answer: C
Clarification: The Dynamic Random Access Memory is the lowest cost, highest density random access memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more compared to SRAM.

2. The memory size of DRAM is ____________
A. 1 to 100 MB
B. 512 to 1024 MB
C. 64 to 512 MB
D. 16 to 256 MB
Answer: D
Clarification: The Dynamic Random Access Memory is the lowest cost, highest density random access memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more compared to SRAM. The memory size of DRAM lies between 16 to 256 MB.

3. The DRAM stores its binary information on __________
A. MOSFET
B. Transistor
C. Capacitor
D. BJT
Answer: C
Clarification: Capacitor has high storing capability only, so DRAM stores its binary information in the form of electric charges on capacitors. However, DRAM takes more time time to access data.

4. Most modern operating systems employ a method of extending RAM capacity, known as __________
A. Magnetic memory
B. Virtual memory
C. Storage memory
D. Static memory
Answer: B
Clarification: Most modern operating systems employ a method of extending RAM capacity, known as virtual memory. Virtual memory is seen as part of main memory but is actually a secondary memory.

5. DRAM uses of integrated MOS capacitors as _______ instead of a flip-flop.
A. Storage cell
B. Memory cell
C. Dynamic cell
D. Static cell
Answer: B
Clarification: DRAM uses of integrated MOS capacitors as memory cell instead of a flip-flop. The advantage of this cell is that it allows very large memory arrays to be constructed on a chip at a lower cost per bit than in static memories.

6. What is the disadvantage of MOS capacitor in DRAM?
A. It can’t hold the data till a long period
B. It doesn’t holds the charge till a long period
C. It is highly densed
D. It is not flexible
Answer: B
Clarification: The disadvantage of MOS capacitor in DRAM is that it can’t hold the stored charge over a long period of time and it has to be refreshed every few millisecond. Thus, DRAM is slow in operation.

7. The dynamic RAM offers __________
A. High power consumption, large storage capacity
B. Reduced power consumption, large storage capacity
C. Reduced power consumption, short storage capacity
D. High power consumption, short storage capacity
Answer: B
Clarification: The dynamic RAM offers reduced power consumption and large storage capacity in a single memory chip. With the availability of such high packing density memory ICs, the capacity of memory will continue to grow. However, it’s access time is more and thus operation is slow.

8. The main memory of a PC is made of __________
A. Cache
B. Dynamic RAM
C. Static RAM
D. Both cache and dynamic RAM
Answer: D
Clarification: The main memory of a PC is made of cache and DRAM. DRAM offers reduced power consumption and large storage capacity in a single memory chip.

9. Virtual memory consists of __________
A. SRAM
B. DRAM
C. Magnetic memory
D. Main Memory
Answer: A
Clarification: Most modern operating systems employ a method of extending RAM capacity, known as virtual memory which consists of SRAM.

10. Dynamic RAM is used as main memory in a computer system as __________
A. It has a lower cell density
B. It needs refreshing circuitry
C. Consumes less power
D. Has higher speed
Answer: D
Clarification: Dynamic RAM is used as main memory in a computer system as it has a higher speed due to the presence of MOSFET technology. However, it’s access time is more compared to SRAM and operation is slow.

11. Cache memory acts between __________
A. RAM and ROM
B. CPU and RAM
C. CPU and Hard Disk
D. CPU and ROM
Answer: B
Clarification: In a computer, cache memory acts between CPU and RAM.

12. Which characteristic of RAM memory makes it not suitable for permanent storage?
A. Unreliable
B. Too slow
C. Too bulky
D. It is volatile
Answer: D
Clarification: RAM is volatile. Therefore, it stores data only as long as the d.c power is on.

13. Why do a DRAM employ the address multiplexing technique?
A. To reduce the number of memory locations
B. To increase the number of memory locations
C. To reduce the number of address lines
D. To increase the number of address lines
Answer: C
Clarification: A Dynamic RAM usually employs a technique called address multiplexing to reduce the number of address lines and thus the number of input/output pins on the IC package.

14. An address multiplexing in DRAM is of _____ bits.
A. 10240
B. 15289
C. 16384
D. 17654
Answer: C
Clarification: A Dynamic RAM usually employs a technique called address multiplexing to reduce the number of address lines and thus the number of input/output pins on the IC package. Address multiplexing has 2¹⁴ = 16384 bits.

15. What is a sense amplifier?
A. It is an amplifier which converts ac current into dc current
B. It is an amplifier which lowers the input voltage
C. It is an amplifier which increases the input voltage
D. It is an amplifier which converts the low voltage to a sufficient voltage
Answer: D
Clarification: A sense amplifier for each column is necessary to convert from the low voltage and low energy to a sufficient level on the I/O data line.

tough questions and answers on all areas of Digital Electronic Circuits,

Digital Electronics/Circuits Multiple Choice Questions on “Number System – 1”.

1. Any signed negative binary number is recognised by its ________
A. MSB
B. LSB
C. Byte
D. Nibble
Answer: A
Clarification: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

2. The parameter through which 16 distinct values can be represented is known as ________
A. Bit
B. Byte
C. Word
D. Nibble
Answer: C
Clarification: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte is a combination of 8 bits. It is “word” that is said to be a collection of 16-bits on most of the systems.

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
A. Dividing
B. Multiplying
C. Adding
D. Subtracting
Answer: B
Clarification: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders.

4. The representation of octal number (532.2)8 in decimal is ________
A. (346.25)10
B. (532.864)10
C. (340.67)10
D. (531.668)10
Answer: A
Clarification: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(532.2)8 = 5 * 8² + 3 * 8¹ + 2 * 8⁰ + 2 * 8^-1 = (346.25)10

5. The decimal equivalent of the binary number (1011.011)2 is ________
A. (11.375)10
B. (10.123)10
C. (11.175)10
D. (9.23)10
Answer: A
Clarification: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
1 * 2³ + 0 * 2² + 1 * 2¹ +1*2⁰ + 0 * 2^-1 +1 * 2^-2 + 1 * 2^-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10

6. An important drawback of binary system is ________
A. It requires very large string of 1’s and 0’s to represent a decimal number
B. It requires sparingly small string of 1’s and 0’s to represent a decimal number
C. It requires large string of 1’s and small string of 0’s to represent a decimal number
D. It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: A
Clarification: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the long binary strings into small parts.

7. The decimal equivalent of the octal number (645)₈ is ______
A. (450)₁₀
B. (451)₁₀
C. (421)₁₀
D. (501)₁₀
Answer: C
Clarification: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
The decimal equivalent of the octal number (645)₈ is 6 * 8² + 4 * 8¹ + 5 * 8⁰ = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 = (421)₁₀.

8. The largest two digit hexadecimal number is ________
A. (FE)16
B. (FD.16
C. (FF)16
D. (EF)16
Answer: C
Clarification: (FE)16 is 254 in decimal system, while (FD.16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.

9. Representation of hexadecimal number (6DE)H in decimal:
A. 6 * 16² + 13 * 16¹ + 14 * 16⁰
B. 6 * 16² + 12 * 16¹ + 13 * 16⁰
C. 6 * 16² + 11 * 16¹ + 14 * 16⁰
D. 6 * 16² + 14 * 16¹ + 15 * 16⁰
Answer: A
Clarification: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 16² + 13 * 16¹ + 14 * 16⁰.

10. The quantity of double word is ________
A. 16 bits
B. 32 bits
C. 4 bits
D. 8 bits
Answer: B
Clarification: One word means 16 bits, Thus, the quantity of double word is 32 bits.