Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “Programmable Read Only Memory -1”.

1. The time from the beginning of a read cycle to the end of tACS/tAA is called as ____________
A. Write enable time
B. Data hold
C. Read cycle time
D. Access time
Answer: D
Clarification: The time from the beginning of a read cycle to the end of tACS/tAA is called as access time. It is the time in which data is fetched from the storage.

2. Why did PROM introduced?
A. To increase the storage capacity
B. To increase the address locations
C. To provide flexibility
D. To reduce the size
Answer: C
Clarification: In order to provide some flexibility in the possible applications of ROM, PROM is introduced. PROM stands for Programmable ROM, in which the ROM is programmed by the user.

3. Which of the following is programmed electrically by the user?
A. ROM
B. EPROM
C. PROM
D. EEPROM
Answer: C
Clarification: Programmable ROMs can be programmed electrically by the user but can’t be reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.

4. PROMs are available in ___________
A. Bipolar and MOSFET technologies
B. MOSFET and FET technologies
C. FET and bipolar technologies
D. MOS and bipolar technologies
Answer: D
Clarification: PROMs (Programmable ROMs) can be programmed electrically by the user but can’t be reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.

5. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ___________
A. 4096
B. 16384
C. 32768
D. 8129
Answer: B
Clarification: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses = 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.

6. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
A. Eight
B. Two
C. One
D. Four
Answer: A
Clarification: RAM stands for Random Access Memory in which any memory address can be accessed in any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.

7. Which of the following best describes the fusible-link PROM?
A. Manufacturer-programmable, reprogrammable
B. Manufacturer-programmable, one-time programmable
C. User-programmable, reprogrammable
D. User-programmable, one-time programmable
Answer: D
Clarification: The fusible-link PROM is user programmable and one time programmable. It means that a written program can not be reprogrammed. EPROMs can be erased and re-programmed.

8. How can ultraviolet erasable PROMs be recognized?
A. There is a small window on the chip
B. They will have a small violet dot next to the #1 pin
C. Their part number always starts with a “U”, such as in U12
D. They are not readily identifiable, since they must always be kept under a small cover
Answer: A
Clarification: An ultraviolet erasable PROMs have small window on the chip with black marked. Such type of PROMS are called EPROMS which are cleared by exposing it to UV radiation. They are re-programmable.

9. Which part of a Flash memory architecture manages all chip functions?
A. Program verify code
B. Floating-gate MOSFET
C. Command code
D. Input/Output pins
Answer: B
Clarification: MOSFET technology is the best one in the manufacturing of chip because it has high flexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory architecture manages all chip functions.

10. How much locations an 8-bit address code can select in memory?
A. 8 locations
B. 256 locations
C. 65,536 locations
D. 131,072 locations
Answer: B
Clarification: An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8 = 256 locations = 2⁸.

11. What is a fusing process?
A. It is a process by which data is passed to the memory
B. It is a process by which data is read through the memory
C. It is a process by which programs are burnout to the diode/transistors
D. It is a process by which data is fetched through the memory
Answer: C
Clarification: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

12. Fusing process is ___________
A. Reversible
B. Irreversible
C. Synchronous
D. Asynchronous
Answer: B
Clarification: Since, any program cannot be reprogrammed in a PROM, so this process is irreversible as PROMs are programmed using the Fusing process. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

13. The cell type used inside a PROM is ___________
A. Link cells
B. Metal cells
C. Fuse cells
D. Electric cells
Answer: C
Clarification: The cell type used inside a PROM is fuse cells by which a program is burnout. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

14. How many types of fuse technologies are used in PROMs?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs. Three types of fuse technologies are used in PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.

15. Metal links are made up of ___________
A. Polycrystalline
B. Magnesium sulphide
C. Nichrome
D. Silicon dioxide
Answer: C
Clarification: Metal links are made up of Nichrome materials.

Digital Electronic Circuits Interview Questions and Answers for freshers on “Logic Gates and Networks-2”.

1. A single transistor can be used to build which of the following digital logic gates?
A. AND gates
B. OR gates
C. NOT gates
D. NAND gates
Answer: C
Clarification: A transistor can be used as a switch. That is when base is low collector is high (input zero, output one) and base is high collector is low (input 1, output 0).

2. How many truth table entries are necessary for a four-input circuit?
A. 4
B. 8
C. 12
D. 16
Answer: D
Clarification: For 4 inputs: 2⁴ = 16 truth table entries are necessary.

3. Which input values will cause an AND logic gate to produce a HIGH output?
A. At least one input is HIGH
B. At least one input is LOW
C. All inputs are HIGH
D. All inputs are LOW
Answer: C
Clarification: For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is high, the output will be high.

4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
A. OR gates only
B. AND gates and NOT gates
C. AND gates, OR gates, and NOT gates
D. OR gates and NOT gates
Answer: C
Clarification: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR gate.

5. The basic logic gate whose output is the complement of the input is the ___________
A. OR gate
B. AND gate
C. INVERTER gate
D. XOR gate
Answer: C
Clarification: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0 becomes 1.

6. The AND function can be used to ___________ and the OR function can be used to _____________
A. Enable, disable
B. Disable, enable
C. Synchronize, energize
D. Detect, invert
Answer: A
Clarification: The AND gate and OR gate are used for enabling and disabling respectively because of their multiplicity and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.

7. The dependency notation “>=1” inside a block stands for which operation?
A. OR
B. XOR
C. AND
D. XNOR
Answer: A
Clarification: The dependency notation “>=1” inside a block stands for OR operation.

8. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
A. LOW
B. HIGH
C. Inverted
D. Floating
Answer: A
Clarification: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it outputs 0.

9. Logic gate circuits contain predictable gate functions that open theirs ____________
A. Outputs
B. Inputs
C. Pre-state
D. Impedance state
Answer: B
Clarification: Logic gate circuits contain predictable gate functions that open their inputs because we are free to give any types of inputs.

10. How many NAND circuits are contained in a 7400 NAND IC?
A. 1
B. 2
C. 4
D. 8
Answer: C
Clarification: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated for the NAND operation. Rest 2 pins for power supply.

for interviews,

Digital Electronics/Circuits Multiple Choice Questions on “Procedure for the Design of Combinational Circuits”.

1. The basic building blocks of the arithmetic unit in a digital computers are ____________
A. Subtractors
B. Adders
C. Multiplexer
D. Comparator
Answer: B
Clarification: The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.

2. A digital system consists of _____ types of circuits.
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: A digital system consists of two types of circuits and these are combinational and sequential logic circuit. Combinational circuits are the ones which do not depend on previous inputs while Sequential circuits depend on past inputs.

3. In a combinational circuit, the output at any time depends only on the _______ at that time.
A. Voltage
B. Intermediate values
C. Input values
D. Clock pulses
Answer: C
Clarification: In a combinational circuit, the output at any time depends only on the input values at that time and not on past or intermediate values.

4. In a sequential circuit, the output at any time depends only on the input values at that time.
A. Past output values
B. Intermediate values
C. Both past output and present input
D. Present input values
Answer: C
Clarification: In a sequential circuit, the output at any time depends on the present input values as well as past output values. It also depends on clock pulses depending whether it’s synchronous or asynchronous sequential circuits.

5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different 
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).

A. B, C, D, E, A
B. A, D, E, B, C
C. A, B, E, C, D
D. B, A, E, C, D
Answer: C
Clarification: Combinational circuits are the ones which do not depend on previous inputs and depends only on the present values. The given arrangement in option c is the right sequence for the designing of the combinational circuits.

6. All logic operations can be obtained by means of ____________
A. AND and NAND operations
B. OR and NOR operations
C. OR and NOT operations
D. NAND and NOR operations
Answer: D
Clarification: Since, the logic gates NOR and NAND are known as universal logic gates, therefore it can be used to design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be obtained by implementation of these gates.

7. The design of an ALU is based on ____________
A. Sequential logic
B. Combinational logic
C. Multiplexing
D. De-Multiplexing
Answer: B
Clarification: The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be broken into identical stages connected in cascade through carries.

8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____ result.
A. Input, zero
B. Output, one
C. Input, one
D. Output, zero
Answer: D
Clarification: If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero result.

9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and ___________
A. An underflow condition
B. A neutral condition
C. An overflow condition
D. One indication
Answer: C
Clarification: If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and an overflow condition.

10. The flag bits in an ALU is defined as ____________
A. The total number of registers
B. The status bit conditions
C. The total number of control lines
D. All of the Mentioned
Answer: B
Clarification: In an ALU, status bit conditions are sometimes called condition code bits or flag bits. It is so called because they tend to represent the status of the respect flags after any operation.

Digital Electronic/Circuits online test on “Parity Generators/Checkers – 2”.

1. Which error detection method uses one’s complement arithmetic?
A. Simple parity check
B. Two-dimensional parity check
C. CRC
D. Checksum
Answer: D
Clarification: A checksum is an error detection method used for the purpose of detecting errors that may have been incorporated during transmission. The checksum can be generated simply by adding bits. Hence, one’s complement arithmetic uses checksum.

2. Which error detection method consists of just one redundant bit per data unit?
A. Simple parity check
B. Two-dimensional parity check
C. CRC
D. Checksum
Answer: A
Clarification: A parity checker is an error detection method used for the purpose of detecting errors that may have been incorporated during transmission. Simple parity check method consists of just one redundant bit per data unit. It is again classified as even parity and odd parity.

3. How many types of parity bits are found?
A. 2
B. 3
C. 4
D. 1
Answer: A
Clarification: There are two types of parity bits, namely even parity and odd parity. In even parity, a 1 bit is added in order to make a group of data bits have even number of 1s. While, in odd parity, a 1 bit is added in order to make a group of data bits have odd number of 1s.

4. What is a parity bit?
A. An error detection is achieved by adding an extra bit
B. After addition, the carry is found
C. Bit generated during data transmission
D. After addition, the total number of bits
Answer: A
Clarification: A simple form of error detection is achieved by adding an extra bit to the transmitted word. The additional bit is known as parity bits.

5. The BCD number 101011 has _______ priority.
A. Even
B. Odd
C. Both even and odd
D. Undefined
Answer: A
Clarification: The given BCD number 101011 has even priority because it has an even number of 1’s (i.e. 4).

6. Which error detection method involves polynomials?
A. Simple parity check
B. CRC
C. Two-dimensional parity check
D. Checksum
Answer: B
Clarification: Cyclic Redundancy Check(CRC. involves parity check polynomials. In the even parity case of CRC, the 1-bit is generated by checking the polynomial x+1.

7. The odd parity output of decimal number 9 is ___________
A. 0
B. 1
C. 1001
D. 0011
Answer: B
Clarification: The odd parity output of decimal number 9 is 1 because the BCD number for 9 is 1001 and it has even number of 1’s.

8. If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is _______
A. Indeterminate
B. 42
C. Even
D. Odd
Answer: A
Clarification: Odd parity bit is 1 when the group of data bits consists of even number of 1s. So to make the group of data bits have odd number of 1s, 1 extra bit is added. If odd parity is used for ASCII error detection, the number of 0s per 8-bit symbol is indeterminate because it is applicable only for 6-bit symbol.

9. Which error detection method can detect a single-bit error?
A. Simple parity check
B. Two-dimensional parity check
C. CRC
D. Checksum
Answer: B
Clarification: A single-bit error can be detected by using two-dimensional parity check method. Since it converts the 4-bit number into 8-bit and count the number of one’s.

10. Which gates are ideal for checking the parity bits?
A. AND
B. NAND
C. EX-OR
D. EX-NOR
Answer: C
Clarification: Exclusive-OR gates are ideal for checking the parity of a binary number because they produce an output when the input has an odd number of 1’s. Therefore, an even-parity input to an EX-OR gate produces a low output, while an odd parity input produces a high output. While, in case of AND, it produces high output when all inputs are 1 else low. Whereas, NAND, does the opposite, by producing low output when all inputs are 1 else high.

Digital Electronics/Circuits Multiple Choice Questions on “Counter Implementation and Applications”.

1. A ripple counter’s speed is limited by the propagation delay of ____________
A. Each flip-flop
B. All flip-flops and gates
C. The flip-flops only with gates
D. Only circuit gates
Answer: A
Clarification: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. The output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

2. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________
A. 12 ms
B. 24 ns
C. 48 ns
D. 60 ns
Answer: D
Clarification: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.

3. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________
A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns
Answer: D
Clarification: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 15ns. So, 4 bits = 15ns * 4 = 60ns.

4. A ripple counter’s speed is limited by the propagation delay of __________
A. Each flip-flop
B. All flip-flops and gates
C. The flip-flops only with gates
D. Only circuit gates
Answer: A
Clarification: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

5. What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
A. 15 ns
B. 22 ns
C. 60 ns
D. 88 ns
Answer: D
Clarification: Maximum propagation delay is the longest delay between an input changing value and the output changing value. Hence, 22 * n = 22*4 (Since there are 4 FFs) = 88ns.

6. The main drawback of a ripple counter is that __________
A. It has a cumulative settling time
B. It has a distributive settling time
C. It has a productive settling time
D. It has an associative settling time
Answer: A
Clarification: The main drawback of a ripple counter is that it has a cumulative settling time (i.e. another bit is transmitted just after one consequently).

7. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the maximum clock frequency that can be used is equal to __________
A. 20 MHz
B. 10 MHz
C. 5 MHz
D. 4 MHz
Answer: C
Clarification: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 50ns. So, 4 bits or FFs = 50ns * 4 = 200ns. Clock frequency = 1/200ns = 5 MHz.

8. As the number of flip flops are increased, the total propagation delay of __________
A. Ripple counter increases but that of synchronous counter remains the same
B. Both ripple and synchronous counters increase
C. Both ripple and synchronous counters remain the same
D. Ripple counter remains the same but that of synchronous counter increases
Answer: A
Clarification: In ripple counter, the clock pulses are applied to one flip-flop only. Hence, as the number of flip-flops increases the delay increases. In the synchronous counter, clock pulses to all flip-flops are applied simultaneously.

9. A reliable method for eliminating decoder spikes is the technique called ________
A. Strobing
B. Feeding
C. Wagging
D. Waving
Answer: A
Clarification: A reliable method for eliminating decoder spikes is the technique called strobing. A strobe signal validates the availability of data on consecutive parallel lines.

10. A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because of __________
A. It is a random event
B. It occurs less frequently than the normal decoded output
C. It is very fast
D. All of the Mentioned
Answer: D
Clarification: A glitch is a transition that occurs before a signal settles to a specific value. A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because it is a random event and very fast and it occurs less frequently than the normal decoded output.

11. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will __________
A. Continue to count with correct outputs
B. Continue to count but have incorrect outputs
C. Stop counting
D. Turn into molten silicon
Answer: C
Clarification: The ripple counter would stop counting because next flip-flop’s input depends on the output of the previous flip-flop.

Digital Electronic/Circuits Problems on “Programmable Read Only Memory-2”.

1. Silicon links are made up of _____________
A. Polycrystalline silicon
B. Polycrystalline magnesium
C. Nichrome
D. Silicon dioxide
Answer: A
Clarification: Metal links are made up of Nichrome materials. Silicon links are made up of polycrystalline silicon.

2. During programming p-n junction is _____________
A. Avalanche reverse biased
B. Avalanche forward biased
C. Zener reverse biased
D. Zener reverse biased
Answer: A
Clarification: The sudden heavy flow of electrons in the reverse direction and heat cause aluminium ions to migrate. So, during programming p-n junction is avalanche reversed biased.

3. The full form of FAMOS is _____________
A. Floating Gate Avalanche Injection MOS
B. Float Gate Avalanche Injection MOS
C. Floating Gate Avalanche Induction MOS
D. Float Gate Avalanche Induction MOS
Answer: A
Clarification: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a floating gate transistor in which the trapped electrons is responsible for the dropping of the voltage.

4. PROM is programmed by _____________
A. EPROM programmer
B. EEPROM programmer
C. PROM programmer
D. ROM programmer
Answer: C
Clarification: PROM is programmed by plugging it into a special device called PROM programmer. The ROM cannot be clear and hence PROM is a one-time programmable device.

5. The PROM starts out with _____________
A. 1s
B. 0s
C. Null
D. Both 1s and 0s
Answer: B
Clarification: PROM is a one-time programmable device, which is programmed by the user. The PROM starts out with all 0s. These current pulses blow the fuse links, thus creating the desire pattern.

6. For the implementation of PROM, which IC is used?
A. IC 74187
B. IC 74186
C. IC 74185
D. IC 74184
Answer: B
Clarification: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

7. IC 74186 is of ______________
A. 1024 bits
B. 32 bits
C. 512 bits
D. 64 bits
Answer: C
Clarification: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.

8. How many memory locations are addressed using 18 address bits?
A. 165,667
B. 245,784
C. 262,144
D. 212,342
Answer: C
Clarification: For n address bits, the memory location will consist of 2ⁿ bits. Using 18 address bits, 2¹⁸ = 262,144 (= 256 K) words are addressed.

9. How many address bits are needed to operate a 2K * 8-bit memory?
A. 10
B. 11
C. 12
D. 13
Answer: B
Clarification: For n address bits, the memory location will consist of 2ⁿ bits. Thus, for 2K, only 11 address bits are required, because 2¹¹ = 2K.

10. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
A. 1024
B. 4096
C. 2048
D. 8192
Answer: D
Clarification: For n address bits, the memory location will consist of 2ⁿ bits. 1024 = 2¹⁰. So, 2¹⁰ * 2³ = 1024 * 8 = 8192 bit.

problems on all areas of Digital Electronic Circuits,