Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “250+ TOP MCQs on Transistor Transistor Logic(TTL or T²L)”.

1. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
A. JFET only
B. Bipolar junction transistors (BJT)
C. Resistors
D. Bipolar junction transistors (BJT) and resistors
Answer: D
Clarification: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. However, resistors have a small role to play and both logic gating and amplifying functions are performed by the transistors.

2. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by ____________
A. Resistors
B. Bipolar junction transistors
C. One transistor
D. Resistors and transistors respectively
Answer: B
Clarification: TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by bipolar junction transistors (BJTs).

3. TTL was invented in 1961 by ____________
A. Baker clamp
B. James L. Buie
C. Chris Brown
D. Frank Wanlass
Answer: B
Clarification: TTL was invented in 1961 by James L Buie.

4. The full form of TCTL is ____________
A. Transistor-coupled transistor logic
B. Transistor-capacitor transistor logic
C. Transistor-complemented transistor logic
D. Transistor-complementary transistor logic
Answer: A
Clarification: The full form of TCTL is transistor-coupled transistor logic.

5. The _______ ancestor to the first personal computers.
A. PARAM 1
B. SATYAM 1
C. KENBAK 1
D. MITS Altair
Answer: C
Clarification: The KENBAK 1, ancestor to the first personal computers.

6. TTL inputs are the emitters of a ____________
A. Transistor-transistor logic
B. Multiple-emitter transistor
C. Resistor-transistor logic
D. Diode-transistor logic
Answer: B
Clarification: TTL inputs are the emitters of a multiple-emitter transistor.

7. TTL is a ____________
A. Current sinking
B. Current sourcing
C. Voltage sinking
D. Voltage sourcing
Answer: A
Clarification: Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 level. Current Sink means it accepts current coming out from a source.

8. Standard TTL circuits operate with a __ volt power supply.
A. 2
B. 4
C. 5
D. 3
Answer: C
Clarification: Standard TTL circuits operate with a 5-volt power supply.

9. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
A. Less
B. More
C. Equal
D. Very High
Answer: B
Clarification: TTL devices consume substantially more power than equivalent CMOS devices at rest. Thus, CMOS devices are faster than TTL devices.

10. A TTL gate may operate inadvertently as an ____________
A. Digital amplifier
B. Analog amplifier
C. Inverter
D. Regulator
Answer: B
Clarification: A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly changing input signal that traverses the unspecified region from 0.7V to 3.3V.

11. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
A. TTL
B. ECL
C. RTL
D. DTL
Answer: A
Clarification: The speed of TTL circuits is limited by the tendency of common emitter circuits to go into saturation due to the injection of minority carriers into the collector region. Hence, it functions slowly compared to CMOS devices.

Digital Electronic/Circuits Quiz on “Fast Adder & Serial Adder – 2”.

1. A serial subtractor can be obtained by converting the serial adder by using the _____________
A. 1’s complement system
B. 2’s complement system
C. 10’s complement
D. 9’s complement
Answer: B
Clarification: A serial subtractor can be obtained by converting the serial adder by using the 2’s complement system. 9’s complement and 10’s complement are used for decimal numbers while adders deal with binary numbers.

2. The hexadecimal number (4B.16 is transmitted as an 8-bit word in parallel. What is the time required for this transmission if the clock frequency is 2.25 MHz?
A. 444 ns
B. 444 s
C. 3.55 s
D. 3.55 ms
Answer: A
Clarification: Because the clock pulse of 4-bit transmits the data of 8-bit word in parallel mode and this transmission is done at 2.25 MHz frequency. We know that: f=1/t and we can find the time required for this transmission by the clock pulse.
Therefore, time = (1/2.25) = 0.4444 us = 444.44 ns ~ 444ns.

3. Internally, a computer’s binary data are always transmitted on parallel channels which is commonly referred to as the __________
A. Parallel bus
B. Serial bus
C. Data bus
D. Memory bus
Answer: C
Clarification: A process consists of 3 types of buses: Control Bus, Data Bus and Address Bus. A computer’s data is always in the binary form which is stored in the bus that transmits the data on any channels. It doesn’t matter that it’s in parallel or serial.

4. What is the frequency of a clock waveform if the period of that waveform is 1.25sec?
A. 8 kHz
B. 0.8 kHz
C. 0.8 MHz
D. 8 MHz
Answer: C
Clarification: By using the formula of frequency, we can find the frequency of clock waveform. Time period(t) of the waveform is = 1.25microseconds
f=1/t
Where ‘t’ is the time taken by the clock waveform;
f=(1/1.25)
so, f=0.8 MHz.

5. Why is parallel data transmission preferred over serial data transmission for most applications?
A. It is much slower
B. It is cheaper
C. More people use it
D. It is much faster
Answer: D
Clarification: Parallel data transmission preferred over serial data transmission for most applications because it is much faster as bits are transmitted simultaneously, whereas in serial data transmission, bits are transmitted one by one.

6. With surface-mount technology (SMT), the devices should __________
A. Utilize transistor outline connections
B. Mount directly
C. Have parallel connecting pins
D. Require holes and pads
Answer: B
Clarification: Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is called a surface-mount device (SMD.. In the industry, it has largely replaced the through-hole technology construction method of fitting components with wire leads into holes in the circuit board. Both technologies can be used on the same board for components not suited to surface mounting such as large transformers and heat-sinked power semiconductors.

7. In most applications, transistor switches used in place of relays?
A. They consume less power
B. They are faster
C. They are quieter and smaller
D. All of the Mentioned
Answer: D
Clarification: Transistors are of less consuming power, faster, quieter, smaller and its implementation is too easy. So, in most applications transistor switches are more preferred. And also, transistors can be current-controlled or voltage-controlled depending on our choice.

8. What can a relay provide between the triggering source and the output that semiconductor switching devices cannot?
A. Total isolation
B. Faster
C. Higher current rating
D. Total isolation and higher current rating
Answer: D
Clarification: A relay provides total isolation and higher current rating between the triggering source and the output that semiconductor switching devices cannot provide. This is why relays are used to drive high watt appliances at offices or other buildings.

9. The serial format for transmitting binary information uses __________
A. A single conductor
B. Multiple conductors
C. Infrared technology
D. Fiber-optic
Answer: A
Clarification: A conductor accepts the whole data and arranges it in a serial manner, which is transmitted as binary information. In serial transmission, data is transmitted bit by bit while in parallel transmission data is transmitted simultaneously.

10. Serial communication can be sped up by __________
A. Using silver or gold conductors instead of copper
B. Using high-speed clock signals
C. Adjusting the duty cycle of the binary information
D. Using silver or gold conductors instead of copper and high-speed clock signals
Answer: B
Clarification: For any serial data transmission there is required of continuously data supply and if the input supply (i.e. high speed clock signals) in a high amount the speed of serial communication can be increased. In serial communication, data is transmitted bit by bit. So the use of high speed clock pulses would make the process faster.

for quizzes,

Digital Electronic/Circuits question bank on “Flip Flops – 3”.

1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
A. Gated JK-latch
B. Gated SR-latch
C. Gated T-latch
D. Gated D-latch
Answer: D
Clarification: Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the number of inputs.

2. The characteristic of J-K flip-flop is similar to _____________
A. S-R flip-flop
B. D flip-flop
C. T flip-flop
D. Gated T flip-flop
Answer: A
Clarification: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is shown by J-K flip-flop.

3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
A. Two AND gates
B. Two NAND gates
C. Two NOT gates
D. Two OR gates
Answer: A
Clarification: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.

4. How is a J-K flip-flop made to toggle?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: D
Clarification: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either set or reset.

5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________
A. Parity error checking
B. Ones catching
C. Digital discrimination
D. Digital filtering
Answer: B
Clarification: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

6. In J-K flip-flop, “no change” condition appears when ___________
A. J = 1, K = 1
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 0, K = 0
Answer: D
Clarification: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.

7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer: D
Clarification: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

8. What is the significance of the J and K terminals on the J-K flip-flop?
A. There is no known significance in their designations
B. The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
C. The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
D. All of the other letters of the alphabet are already in use
Answer: C
Clarification: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the toggling of states.

9. On a J-K flip-flop, when is the flip-flop in a hold condition?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: A
Clarification: At J=0 k=0 output continues to be in the same state. This is the memory storing state.

10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________
A. 00
B. 11
C. 01
D. 10
Answer: A
Clarification: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 2² = 4). So after 4 clock pulses the O/P repeats i.e. 00.

11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
A. 1 kHz
B. 2 kHz
C. 4 kHz
D. 16 kHz
Answer: B
Clarification: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop. Since the output frequency is determined on basis of the 4^th flip-flop.

12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz
Answer: B
Clarification: 12 flip flops = 2¹² = 4096
Input Clock frequency = 20.48*10⁶ = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

13. How many flip-flops are in the 7475 IC?
A. 2
B. 1
C. 4
D. 8
Answer: C
Clarification: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.

Digital Electronic Circuits question bank,

Digital Electronics/Circuits Multiple Choice Questions on “Ring Counter”.

1. Ring shift and Johnson counters are ____________
A. Synchronous counters
B. Asynchronous counters
C. True binary counters
D. Synchronous and true binary counters
Answer: A
Clarification: Synchronous counters are the counters being triggered in the presence of a clock pulse. Since all of the clock inputs are connected through a single clock pulse in ring shift and johnson counters. So, both are synchronous counters.

2. What is the difference between a shift-right register and a shift-left register?
A. There is no difference
B. The direction of the shift
C. Propagation delay
D. The clock input
Answer: B
Clarification: In shift-right register, shifting of bit takes place towards the right and towards left for shift-left register. Thus, both the registers vary in the shifting of their direction.

3. What is a transceiver circuit?
A. A buffer that transfers data from input to output
B. A buffer that transfers data from output to input
C. A buffer that can operate in both directions
D. A buffer that can operate in one direction
Answer: C
Clarification: A transceiver circuit is a buffer that can operate in both directions right as well as left.

4. A 74HC195 4-bit parallel access shift register can be used for ____________
A. Serial in/serial out operation
B. Serial in/parallel out operation
C. Parallel in/serial out operation
D. All of the Mentioned
Answer: D
Clarification: 74HC195 is an IC, which can be used for all of the given operations, as well as for, parallel-in/parallel-out.

5. Which type of device may be used to interface a parallel data format with external equipment’s serial format?
A. UART
B. Key matrix
C. Memory chip
D. Series in Parallel out
Answer: A
Clarification: UART means Universal Asynchronous Receiver/Transmitter which converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmission. And also receives data in serial form and converts it into parallel form and sent to the processor.

6. What is the function of a buffer circuit?
A. To provide an output that is inverted from that on the input
B. To provide an output that is equal to its input
C. To clean up the input
D. To clean up the output
Answer: B
Clarification: The function of a buffer circuit is to provide an output that is equal to its input. A transceiver circuit is a buffer that can operate in both directions right as well as left.

7. What is the preset condition for a ring shift counter?
A. All FFs set to 1
B. All FFs cleared to 0
C. A single 0, the rest 1
D. A single 1, the rest 0
Answer: D
Clarification: A ring shift counter is a counter in which the output of one FF connected to the input of the adjacent FF. In preset condition, all of the bits are 0 except first one.

8. Which is not characteristic of a shift register?
A. Serial in/parallel in
B. Serial in/parallel out
C. Parallel in/serial out
D. Parallel in/parallel out
Answer: A
Clarification: There is no such type of register present who doesn’t have output end. Thus, Serial in/Parallel in is not a characteristic of a shift register. There has to be an output, be it serial or parallel.

9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ____________
A. Divide-by-4 clock pulse
B. Sequence generator
C. Strobe line
D. Multiplexer
Answer: C
Clarification: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals on adjacent parallel lines. Thus, in registers the strobe line is there to check the availability of data.

10. Another way to connect devices to a shared data bus is to use a ____________
A. Circulating gate
B. Transceiver
C. Bidirectional encoder
D. Strobed latch
Answer: B
Clarification: A transceiver is a device comprising both a transmitter and a receiver which are combined and share common circuitry or a single housing. When no circuitry is common between transmit and receive functions, the device is a transmitter-receiver.

Digital Electronics/Circuits Multiple Choice Questions on “Emitter-Coupled Logic(ECL)”.

1. The full form of ECL is __________
A. Emitter-collector logic
B. Emitter-complementary logic
C. Emitter-coupled logic
D. Emitter-cored logic
Answer: C
Clarification: The full form of ECL is emitter-coupled logic.

2. Which logic is the fastest of all the logic families?
A. TTL
B. ECL
C. HTL
D. DTL
Answer: B
Clarification: ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results in the highest transmission rate.

3. The full form of CML is __________
A. Complementary mode logic
B. Current mode logic
C. Collector mode logic
D. Collector Mixed Logic
Answer: C
Clarification: The full form of CML is Collector Mode Logic.

4. Sometimes ECL can also be named as __________
A. EEL
B. CEL
C. CML
D. CCL
Answer: C
Clarification: ECL (Emitter Coupled LogiC. can also be named as CML(Collector Mode LogiC..

5. In an ECL the output is taken from __________
A. Emitter
B. Base
C. Collector
D. Junction of emitter and base
Answer: C
Clarification: Though, the emitter and collector of the ECL are coupled together. So, the output will be taken from a collector.

6. The ECL behaves as __________
A. NOT gate
B. NOR gate
C. NAND gate
D. AND gate
Answer: B
Clarification: The ECL behaves as NOR gate because if any of the input voltages go high as compared to the reference voltage, the output is low and the output is high only when all the input voltages are low.

7. In ECL the fanout capability is __________
A. High
B. Low
C. Zero
D. Sometimes high and sometimes low
Answer: A
Clarification: If the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of inputs that a single gate output can accept.

8. ECL’s major disadvantage is that __________
A. It requires more power
B. It’s fanout capability is high
C. It creates more noise
D. It is slow
Answer: A
Clarification: ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families. But ECL logic gates have clock frequency. Thus, they have a fast operation.

9. The full form of SCFL is __________
A. Source-collector logic
B. Source-coupled logic
C. Source-complementary logic
D. Source Cored Logic
Answer: B
Clarification: The full form of SCFL is source-coupled logic.

10. The equivalent of emitter-coupled logic made out of FETs is called __________
A. CML
B. SCFL
C. FECL
D. EFCL
Answer: B
Clarification: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL). Like ECL, SCL is also the fastest among the logic families.

11. ECL was invented in _______ by __________
A. 1956, Baker clamp
B. 1976, James R. Biard
C. 1956, Hannon S. Yourke
D. 1976, Yourke
Answer: C
Clarification: ECL was invented in August 1956 at IBM by Hannon S Yourke.

12. At the time of invention, an ECL was called as __________
A. Source-coupled logic
B. Current Mode Logic
C. Current-steering logic
D. Emitter-coupled logic
Answer: C
Clarification: At the time of invention, an ECL was called a current-steering logic because it involved current switching.

13. The ECL circuits usually operates with __________
A. Negative voltage
B. Positive voltage
C. Grounded voltage
D. High Voltage
Answer: A
Clarification: The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to grounD., in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.

14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
A. ECL
B. VECL
C. PECL
D. LECL
Answer: C
Clarification: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V instead of 5 V supply.