Category: Digital Circuits Objective Questions

250+ TOP MCQs on Counters and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Counters”.

1. In digital logic, a counter is a device which ____________
A. Counts the number of outputs
B. Stores the number of times a particular event or process has occurred
C. Stores the number of times a clock pulse rises and falls
D. Counts the number of inputs
Answer: B
Clarification: In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

2. A counter circuit is usually constructed of ____________
A. A number of latches connected in cascade form
B. A number of NAND gates connected in cascade form
C. A number of flip-flops connected in cascade
D. A number of NOR gates connected in cascade form
Answer: C
Clarification: A counter circuit is usually constructed of a number of flip-flops connected in cascade. Preferably, JK Flip-flops are used to construct counters and registers.

3. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
A. 0 to 2n
B. 0 to 2n + 1
C. 0 to 2n – 1
D. 0 to 2n+1/2
Answer: C
Clarification: The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will count till 22-1 = 3. Thus, it will count from 0 to 3.

4. How many types of the counter are there?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter and such like.

5. A decimal counter has ______ states.
A. 5
B. 10
C. 15
D. 20
Answer: B
Clarification: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also known as Decade Counter counting from 0 to 9.

6. Ripple counters are also called ____________
A. SSI counters
B. Asynchronous counters
C. Synchronous counters
D. VLSI counters
Answer: B
Clarification: Ripple counters are also called asynchronous counter. In Asynchronous counters, only the first flip-flop is connected to an external clock while the rest of the flip-flops have their preceding flip-flop output as clock to them.

7. Synchronous counter is a type of ____________
A. SSI counters
B. LSI counters
C. MSI counters
D. VLSI counters
Answer: C
Clarification: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous Counters, the clock pulse is supplied to all the flip-flops simultaneously.

8. Three decade counter would have ____________
A. 2 BCD counters
B. 3 BCD counters
C. 4 BCD counters
D. 5 BCD counters
Answer: B
Clarification: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.

9. BCD counter is also known as ____________
A. Parallel counter
B. Decade counter
C. Synchronous counter
D. VLSI counter
Answer: B
Clarification: BCD counter is also known as decade counter because both have the same number of stages and both count from 0 to 9.

10. The parallel outputs of a counter circuit represent the _____________
A. Parallel data word
B. Clock frequency
C. Counter modulus
D. Clock count
Answer: D
Clarification: The parallel outputs of a counter circuit represent the clock count. A counter counts the number of times an event takes place in accordance to the clock pulse.

250+ TOP MCQs on Introduction of Memory Devices – 5 and Answers

Digital Electronic Circuits Questions & Answers for campus interviews on “Introduction of Memory Devices-5”.

1. When two or more devices try to write data in a bus simultaneously, is known as ______________
A. Bus collisions
B. Address multiplexing
C. Address decoding
D. Bus contention
Answer: D
Clarification: Bus contention is an undesirable state of the bus of a computer, in which more than one memory mapped device or the CPU is attempting to place output values onto the bus at once.

2. A memory is a collection of ____________
A. Unit cells
B. Storage cells
C. Data cells
D. Binary cells
Answer: B
Clarification: A memory is a collection of storage cells with associated circuits needed to transfer information.

3. To transfer the information from input to output and vice versa, the cells used are ____________
A. Storage cells
B. Data cells
C. Unit cells
D. Both data and unit cells
Answer: A
Clarification: To transfer the information from input to output and vice versa, the cells used are called storage cells. The storage cells stores data in the form of binary information.

4. The data stored in a group of bits is called ____________
A. Nibble
B. Word
C. Byte
D. Address
Answer: B
Clarification: The data stored in a group of bits is called word. Usually, a word is a group of 16-bits or 2-bytes.

5. Each word consist of a sequence of ____________
A. Letters
B. Binary numbers
C. Hexadecimal numbers
D. Gray codes
Answer: B
Clarification: Each word consists of a sequence of 0s and 1s (i.e. binary numbers). Usually, a word is a group of 16-bits or 2-bytes.

6. Each word stored in a memory location is represented by ____________
A. RAM
B. ROM
C. Storage class
D. Address
Answer: D
Clarification: Each word stored in a memory location is represented by address. Usually, a word is a group of 16-bits or 2-bytes.

7. The group of each 8-bit is called ____________
A. Nibble
B. Flag
C. Byte
D. Word
Answer: C
Clarification: 1 byte = 8-bit, 4-bits = 1 nibble and 16-bits = 1 word.

8. The capacity of a memory unit is ____________
A. The number of binary input stored
B. The number of words stored
C. The number of bytes stored
D. All of the Mentioned
Answer: C
Clarification: The total number of bytes that can be stored, is the maximum capacity of a memory unit. However, memory unit is the smallest unit of a processor.

9. The communication between memory and its environment is achieved through ____________
A. Control lines
B. Data input/output lines
C. Address selection lines
D. All of the Mentioned
Answer: D
Clarification: Firstly, the data input is needed to transfer the information and it is passed through the address lines and then controlled by control lines. The control lines are responsible for the timing and control of the signals sent and received.

10. One of the most important specifications on magnetic media is the ____________
A. Polarity reversal rate
B. Tracks per inch
C. Data transfer rate
D. Rotation speed
Answer: C
Clarification: The rate of data transfer depends on the properties of magnetic media.

for campus interviews,

250+ TOP MCQs on Sum of Products and Products of Sum and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Sum of Products and Products of Sum”.

1. The logical sum of two or more logical product terms is called __________
A. SOP
B. POS
C. OR operation
D. NAND operation
Answer: A
Clarification: The logical sum of two or more logical product terms, is called SOP (i.e. sum of product). The logical product of two or more logical sum terms is called POS (i.e. product of sums).

2. The expression Y=AB+BC+AC shows the _________ operation.
A. EX-OR
B. SOP
C. POS
D. NOR
Answer: B
Clarification: The given expression has the operation product as well as the sum of that. So, it shows SOP operation. POS will be the product of sum terms.

3. The expression Y=(A+B.(B+C.(C+A. shows the _________ operation.
A. AND
B. POS
C. SOP
D. NAND
Answer: B
Clarification: The given expression has the operation sum as well as the product of that. So, it shows POS(product of sum) operation. SOP will be the sum of product terms.

4. A product term containing all K variables of the function in either complemented or uncomplemented form is called a __________
A. Minterm
B. Maxterm
C. Midterm
D. ∑ term
Answer: A
Clarification: A product term containing all K variables of the function in either complemented or uncomplemented form is called a minterm. A sum term containing all K variables of the function in either complemented or uncomplemented form is called a maxterm.

5. According to the property of minterm, how many combination will have value equal to 1 for K input variables?
A. 0
B. 1
C. 2
D. 3
Answer: B
Clarification: The main property of a minterm is that it possesses the value 1 for only one combination of K input variables and the remaining will have the value 0.

6. The canonical sum of product form of the function y(A,B. = A + B is __________
A. AB + BB + A’A
B. AB + AB’ + A’B
C. BA + BA’ + A’B’
D. AB’ + A’B + A’B’
Answer: B
Clarification: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ + A’B.

7. A variable on its own or in its complemented form is known as a __________
A. Product Term
B. Literal
C. Sum Term
D. Word
Answer: B
Clarification: A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.

8. Maxterm is the sum of __________ of the corresponding Minterm with its literal complemented.
A. Terms
B. Words
C. Numbers
D. Nibble
Answer: A
Clarification: Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.

9. Canonical form is a unique way of representing ____________
A. SOP
B. Minterm
C. Boolean Expressions
D. POS
Answer: C
Clarification: Boolean Expressions are represented through a canonical form. An example of canonical form is A’B’C’ + AB’C + ABC’.

10. There are _____________ Minterms for 3 variables (a, b, C..
A. 0
B. 2
C. 8
D. 1
Answer: C
Clarification: Minterm is given by 2n. So, 23 = 8 minterms are required.

11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.
A. POS
B. Literals
C. SOP
D. POS
Answer: C
Clarification: SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.

250+ TOP MCQs on Compatibility or Interfacing and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Compatibility or Interfacing”.

1. Compatibility refers to ____________
A. The output of a circuit should match with the input of another circuit
B. The output of a circuit should match with the input of the same circuit
C. The input of a circuit should match with the output of another circuit
D. The input of a circuit should match with the output of same circuit

Answer: A
Clarification: The output(s) of a circuit or a system should match the input(s) of another circuit or system that has different electrical characteristics. This is referred to as compatibility.

2. The method of connecting a driving device to a loading device is known as ___________
A. Compatibility
B. Interface
C. Sourcing
D. Sinking

Answer: B
Clarification: The method of connecting a driving device to a loading device is known as interface. The output(s) of a circuit or a system should match the input(s) of another circuit or system that has different electrical characteristics. This is referred to as compatibility.

3. The first CML logic was introduced by General Electric in ___________
A. 1960
B. 1981
C. 1961
D. 1990

Answer: C
Clarification: CML stands for Current Mode Logic. The first CML logic was introduced by General Electric in 1961.

4. Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they ___________
A. Produces too much noise
B. Consume too much power
C. Have high fan-in
D. Have high fan-out

Answer: B
Clarification: Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they consume too much power. CMOS consumes the least power while TTL provides high speed.

5. The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from ___________
A. Fan-in
B. Fan-out
C. Saturation
D. Cut-off

Answer: C
Clarification: The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from saturation. In Saturation mode, the transistor is in “ON”mode, where it seems like a short circuit between collector and emitter.

6. Schottky families prevent the saturating using ___________
A. Transistors
B. Schottky transistors
C. Diodes
D. Schottky diodes

Answer: D
Clarification: Schottky families prevent the saturating using Schottky diodes across the base-collector junctions of transistors. In Saturation mode, the transistor is in “ON”mode, where it seems like a short circuit between collector and emitter.

7. The basic idea of basic CML circuit came from an ___________
A. Inverter
B. Buffer
C. Transistor
D. Both inverter and buffer

Answer: D
Clarification: CML is Current Mode Logic in which data is transmitted at high speed of Mbps. Since this circuit has both inverting and non-inverting output. So, It behaves like an inverter/buffer.

8. The full form of MECL is ___________
A. Mono emitter coupled logic
B. Motorola emitter coupled logic
C. Motorola emitter capacitor logic
D. Both mono emitter and motorola coupled logic

Answer: B
Clarification: The full form of MECL is Motorola emitter coupled logic. ECL is a high speed BJT. It uses BJT differential amplifier with single input and restricted current to avoid the transistor going into saturation and thus turning off operation.

9. Motorola has offered MECL circuits in ______ logic families.
A. 3
B. 4
C. 5
D. 6

Answer: C
Clarification: Motorola has offered MECL circuits in five logic families: MECL I, MECL II, MECL III, MECL 10000 (MECL 10K) and MECL 10H000 (MECL 10KH). The full form of MECL is Motorola emitter coupled logic. ECL is a high speed BJT. It uses BJT differential amplifier with single input and restricted current to avoid the transistor going into saturation and thus turning off operation.

10. The latest entrant to the ECL family is ___________
A. ECL 10K
B. ECL 100K
C. ECL 1000K
D. ECL 10000K

Answer: B
Clarification: The latest entrant to the ECL family is ECL 100K, having 6-digit part numbers. This family offers functions, in general, different from those offered by 10K series. This family operates with a reduced power supply voltage -4.5 V, has shorter propagation delay of 0.75 ns, and transition time of 0.7 ns. However, the power consumption per gate is about 40 mW.

11. All input of NOR as low produces result as ___________
A. Low
B. Mid
C. High
D. High Impedance

Answer: C
Clarification: According to the properties of NOR gate, if all the input of NOR as low produces a result as high. While if any input of NOR is high, then it produces low output.

12. In RTL NOR gate, the output is at logic 1 only when all the inputs are at ___________
A. logic 0
B. logic 1
C. +10v
D. floating

Answer: A
Clarification: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at logic 0. The output of NOR will be 0 if any of the input is 1.

250+ TOP MCQs on Demultiplexers (Data Distributors) – 2 and Answers

Digital Electronic/Circuits Multiple Choice Questions & Answers on “Demultiplexers(Data Distributors) – 2”.

1. Why is a demultiplexer called a data distributor?
A. The input will be distributed to one of the outputs
B. One of the inputs will be selected for the output
C. The output will be distributed to one of the inputs
D. Single input gives single output
Answer: A
Clarification: A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why it is called a data distributor.

2. Most demultiplexers facilitate which type of conversion?
A. Decimal-to-hexadecimal
B. Single input, multiple outputs
C. AC to DC
D. Odd parity to even parity
Answer: B
Clarification: A demultiplexer sends a single input to multiple outputs, depending on the select lines. Demultiplexer converts single input into multiple outputs.

3. In 1-to-4 demultiplexer, how many select lines are required?
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.

4. In a multiplexer the output depends on its ____________
A. Data inputs
B. Select inputs
C. Select outputs
D. Enable pin
Answer: B
Clarification: A demultiplexer sends a single input to multiple outputs, depending on the select lines. As the select input changes, the output of the multiplexer varies according to that input.

5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________
A. Y0
B. Y1
C. Y2
D. Y3
Answer: D
Clarification: It can be calculated from the figure shown below:
digital-circuits-multiple-choice-questions-answers-q5
For C0 =1 and C1 =1, Y3 will be the output as 0 and 1 are the bit combinations of 1.

6. How many select lines are required for a 1-to-8 demultiplexer?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: The formula for total no. of outputs is given by 2n, where n is the no. of select lines. In this case n = 3 since 23 = 8.

7. How many AND gates are required for a 1-to-8 multiplexer?
A. 2
B. 6
C. 8
D. 5
Answer: C
Clarification: The number of AND gates required will be equal to the number of outputs in a demultiplexer, which are 8.

8. Which IC is used for the implementation of 1-to-16 DEMUX?
A. IC 74154
B. IC 74155
C. IC 74139
D. IC 74138
Answer: A
Clarification: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

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250+ TOP MCQs on Asynchronous Counter and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Asynchronous Counter”.

1. How many natural states will there be in a 4-bit ripple counter?
A. 4
B. 8
C. 16
D. 32
Answer: C
Clarification: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

2. A ripple counter’s speed is limited by the propagation delay of _____________
A. Each flip-flop
B. All flip-flops and gates
C. The flip-flops only with gates
D. Only circuit gates
Answer: A
Clarification: A ripple counter is something that is derived by other flip-flops. It’s like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

3. One of the major drawbacks to the use of asynchronous counters is that ____________
A. Low-frequency applications are limited because of internal propagation delays
B. High-frequency applications are limited because of internal propagation delays
C. Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications
D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications
Answer: B
Clarification: One of the major drawbacks to the use of asynchronous counters is that High-frequency applications are limited because of internal propagation delays. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

4. Internal propagation delay of asynchronous counter is removed by ____________
A. Ripple counter
B. Ring counter
C. Modulus counter
D. Synchronous counter
Answer: D
Clarification: Propagation delay refers to the amount of time taken in producing an output when the input is altered. Internal propagation delay of asynchronous counter is removed by synchronous counter because clock input is given to each flip-flop individually in synchronous counter.

5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
A. The output increases by 1
B. The output decreases by 1
C. The output word increases by 2
D. The output word decreases by 2
Answer: B
Clarification: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop is given to second flip-flop as clock input. So, in case of binary down counter the output word decreases by 1.

6. How many flip-flops are required to construct a decade counter?
A. 4
B. 8
C. 5
D. 10
Answer: A
Clarification: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8, therefore, 4 flip flops needed.

7. The terminal count of a typical modulus-10 binary counter is ____________
A. 0000
B. 1010
C. 1001
D. 1111
Answer: C
Clarification: A binary counter counts or produces the equivalent binary number depending on the cycles of the clock input. Modulus-10 means count from 0 to 9. So, the terminal count is 9 (1001).

8. How many different states does a 3-bit asynchronous counter have?
A. 2
B. 4
C. 8
D. 16
Answer: C
Clarification: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

9. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________
A. 12 ms
B. 24 ns
C. 48 ns
D. 60 ns
Answer: D
Clarification: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.

10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?
A. 1
B. 2
C. 8
D. 15
Answer: D
Clarification: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore, transition states = 24 – 1 = 15. So, total transitional states are 15.

11. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns
Answer: D
Clarification: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.

12. Three cascaded decade counters will divide the input frequency by ____________
A. 10
B. 20
C. 100
D. 1000
Answer: D
Clarification: Decade counter has 10 states. So, three decade counters are cascaded i.e. 10*10*10=1000 states.

13. A ripple counter’s speed is limited by the propagation delay of ____________
A. Each flip-flop
B. All flip-flops and gates
C. The flip-flops only with gates
D. Only circuit gates
Answer: A
Clarification: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.

14. A 4-bit counter has a maximum modulus of ____________
A. 3
B. 6
C. 8
D. 16
Answer: D
Clarification: In a n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

15. A principle regarding most display decoders is that when the correct input is present, the related output will switch ____________
A. HIGH
B. To high impedance
C. To an open
D. LOW
Answer: D
Clarification: A principle regarding most display decoders is that when the correct input is present, the related output will switch LOW. Since it’s an active-low device.