Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “Half & Full Subtractor”.

1. Half subtractor is used to perform subtraction of ___________
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Answer: A
Clarification: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.

2. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
A. Carry
B. Borrow
C. Input
D. Output
Answer: B
Clarification: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during addition process.

3. How many outputs are required for the implementation of a subtractor?
A. 1
B. 2
C. 3
D. 4
Answer: B
Clarification: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.

4. Let the input of a subtractor is A and B then what the output will be if A = B?
A. 0
B. 1
C. A
D. B
Answer: A
Clarification: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the output.

5. Let A and B is the input of a subtractor then the output will be ___________
A. A XOR B
B. A AND B
C. A OR B
D. A EXNOR B
Answer: A
Clarification: The subtractor has two outputs BORROW and DIFFERENCE. Since the difference output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final difference output is AB’ + BA’.

6. Let A and B is the input of a subtractor then the borrow will be ___________
A. A AND B’
B. A’ AND B
C. A OR B
D. A AND B
Answer: B
Clarification: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A’ AND B..

7. What does minuend and subtrahend denotes in a subtractor?
A. Their corresponding bits of input
B. Its outputs
C. Its inputs
D. Borrow bits
Answer: C
Clarification: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called minuend and B as subtrahend.

8. Full subtractor is used to perform subtraction of ___________
A. 2 bits
B. 3 bits
C. 4 bits
D. 8 bits
Answer: B
Clarification: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.

9. The full subtractor can be implemented using ___________
A. Two XOR and an OR gates
B. Two half subtractors and an OR gate
C. Two multiplexers and an AND gate
D. Two comparators and an AND gate
Answer: B
Clarification: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR gate.

10. The output of a subtractor is given by (if A, B and X are the inputs).
A. A AND B XOR X
B. A XOR B XOR X
C. A OR B NOR X
D. A NOR B XOR X
Answer: B
Clarification: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.

11. The output of a full subtractor is same as ____________
A. Half adder
B. Full adder
C. Half subtractor
D. Decoder
Answer: B
Clarification: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C., respectively.

Digital Electronics/Circuits Multiple Choice Questions on “Parity Generators/Checkers – 1”.

1. How many outputs are present in a BCD decoder?
A. 4
B. 5
C. 15
D. 10
Answer: D
Clarification: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2ⁿ outputs. A BCD to Decimal decoder has 10 number of outputs because the decimal digit’s range is from 0 to 9.

2. Which digital system translates coded characters into a more useful form?
A. Encoder
B. Display
C. Counter
D. Decoder
Answer: D
Clarification: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2ⁿ outputs. Decoder converts the coded characters into our required data form.

3. What control signals may be necessary to operate a 1-line-to-16 line decoder?
A. Flasher circuit control signal
B. A LOW on all gate enable inputs
C. Input from a hexadecimal counter
D. A HIGH on all gate enable circuits
Answer: B
Clarification: A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder because enable pins are usually, active-low pins.

4. How many inputs are required for a 1-of-10 BCD decoder?
A. 4
B. 8
C. 10
D. 2
Answer: A
Clarification: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2ⁿ outputs. Therefore, for a BCD to decimal decoder, No. of inputs = 4 such that number of outputs is <= 2ⁿ.

5. A BCD decoder will have how many rows in its truth table?
A. 10
B. 9
C. 8
D. 3
Answer: A
Clarification: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2ⁿ outputs. Thus, BCD decoder will have 10 rows as it’s input ranges from 0 to 9.

6. How many possible outputs would a decoder have with a 6-bit binary input?
A. 32
B. 64
C. 128
D. 16
Answer: C
Clarification: The possible outputs would be: 2ⁿ = 64 (Since n = 6 here).

7. Which is the way to convert BCD to binary using the hardware approach?
A. By using MSI IC circuits
B. By using a keyboard encoder
C. By using an ALU
D. By using UART
Answer: A
Clarification: One way to convert BCD to binary using the hardware approach is MSI (medium scale integration) IC circuits.

8. How many inputs are required for a 1-of-16 decoder?
A. 2
B. 16
C. 8
D. 4
Answer: D
Clarification: A binary decoder is a combinational logic circuit which decodes binary information from n-inputs to a maximum of 2ⁿ outputs. Here, number of outputs = 16.
16 = 2⁴ = 2ⁿ. Thus, number of inputs is 4.

9. A truth table with output columns numbered 0–15 may be for which type of decoder IC?
A. Hexadecimal 1-of-16
B. Dual octal outputs
C. Binary-to-hexadecimal
D. Hexadecimal-to-binary
Answer: A
Clarification: A binary decoder is a combinational logic circuit that decodes binary information from n-inputs to a maximum of 2ⁿ outputs. A truth table with output columns numbered 0–15 may be for Hexadecimal 1-of-16. Because hexadecimal occupies less space in a system.

10. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol?
A. A bubble indicates active-HIGH
B. A bubble indicates active-LOW
C. A triangle indicates active-HIGH
D. A triangle indicates active-LOW
Answer: B
Clarification: A bubble indicates active-LOW in a decoder always. Enable pin of the decoder is usually active-LOW and is triggered on the input being at 0.

Digital Electronics/Circuits Multiple Choice Questions on “Propagation Delay in Ripple Counter”.

1. Modulus refers to ____________
A. A method used to fabricate decade counter units
B. The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
C. An input on a counter that is used to set the counter state, such as UP/DOWN
D. The maximum number of states in a counter sequence
Answer: D
Clarification: Modulus is defined as the maximum number of stages/states a counter has. It is independent of the number of states the counter will actually traverse.

2. A sequential circuit design is used to ____________
A. Count up
B. Count down
C. Decode an end count
D. Count in a random order
Answer: D
Clarification: A sequential circuit design is used to count in a random manner which is faster than the combinational circuit. It is used for storing data.

3. In general, when using a scope to troubleshoot digital systems, the instrument should be triggered by ____________
A. The A channel or channel 1
B. The vertical input mode, when using more than one channel
C. The system clock
D. Line sync, in order to observe troublesome power line glitches
Answer: C
Clarification: All the information is sent from one end to another end through the clock pulse which behaves like a carrier. So, for troubleshooting it should be triggered by the same. Since the system clock is internally produced.

4. Which counters are often used whenever pulses are to be counted and the results displayed in decimal?
A. Synchronous
B. Bean
C. Decade
D. BCD
Answer: D
Clarification: BCD means Binary Coded Decimal, which means that decimal numbers coded of binary numbers. It displays the decimal equivalent of corresponding binary numbers.

5. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
A. 74134
B. LPM
C. Synchronous
D. AHDL
Answer: B
Clarification: The library of parameterized modules (LPM) counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

6. The minimum number of flip-flops that can be used to construct a modulus-5 counter is ____________
A. 3
B. 8
C. 5
D. 10
Answer: A
Clarification: The minimum number of flip-flops used in a counter is given by: 2^(n-1)<=N<=2ⁿ.
Thus, for modulus-5 counter: 2² <= N <= 2³, where N = 5 and n = 3.

7. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ____________
A. 20%
B. 50%
C. 10%
D. 80%
Answer: A
Clarification: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty cycle is 2/10*100 = 20%. Since the duty cycle is the ratio of on-time to the total time.

8. Normally, the synchronous counter is designed using ____________
A. S-R flip-flops
B. J-K flip-flops
C. D flip-flops
D. T flip-flops
Answer: B
Clarification: Since J-K flip-flops have options of recovery from toggle condition and by using less number of J-K flip-flops a synchronous counter can be designed. So, it is more preferred. Also, because JK-flip-flops resolves the problem of Forbidden States.

9. MOD-16 counter requires ________ no. of states.
A. 8
B. 4
C. 16
D. 32
Answer: C
Clarification: 2ⁿ >= N >= 2^(n-1), by using this formula we get the value of N=16 for n=4.

10. What is a state diagram?
A. It provides the graphical representation of states
B. It provides exactly the same information as the state table
C. It is same as the truth table
D. It is similar to the characteristic equation
Answer: B
Clarification: The state diagram provides exactly the same information as the state table and is obtained directly from the state table.

11. High speed counter is ____________
A. Ring counter
B. Ripple counter
C. Synchronous counter
D. Asynchronous counter
Answer: C
Clarification: Synchronous counter doesn’t have propagation delay. Propagation delay refers to the amount of time taken in producing the output when the input is altered.

12. Program counter in a digital computer ____________
A. Counts the number of programs run in the machine
B. Counts the number of times a subroutine
C. Counts the number of time the loops are executed
D. Points the memory address of the current or the next instruction
Answer: D
Clarification: Program counter in a digital computer points the memory address of the current or the next instruction which is to be executed.

13. Fundamental mode is another name for ____________
A. Level operation
B. Pulse operation
C. Clock operation
D. Edge operation
Answer: B
Clarification: Whatever the input given to the devices are in the form of pulses always. That is why it is known as a fundamental mode.

Digital Electronics/Circuits Multiple Choice Questions on “Programmable Read Only Memory -1”.

1. The time from the beginning of a read cycle to the end of tACS/tAA is called as ____________
A. Write enable time
B. Data hold
C. Read cycle time
D. Access time
Answer: D
Clarification: The time from the beginning of a read cycle to the end of tACS/tAA is called as access time. It is the time in which data is fetched from the storage.

2. Why did PROM introduced?
A. To increase the storage capacity
B. To increase the address locations
C. To provide flexibility
D. To reduce the size
Answer: C
Clarification: In order to provide some flexibility in the possible applications of ROM, PROM is introduced. PROM stands for Programmable ROM, in which the ROM is programmed by the user.

3. Which of the following is programmed electrically by the user?
A. ROM
B. EPROM
C. PROM
D. EEPROM
Answer: C
Clarification: Programmable ROMs can be programmed electrically by the user but can’t be reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.

4. PROMs are available in ___________
A. Bipolar and MOSFET technologies
B. MOSFET and FET technologies
C. FET and bipolar technologies
D. MOS and bipolar technologies
Answer: D
Clarification: PROMs (Programmable ROMs) can be programmed electrically by the user but can’t be reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.

5. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is ___________
A. 4096
B. 16384
C. 32768
D. 8129
Answer: B
Clarification: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses = 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.

6. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
A. Eight
B. Two
C. One
D. Four
Answer: A
Clarification: RAM stands for Random Access Memory in which any memory address can be accessed in any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.

7. Which of the following best describes the fusible-link PROM?
A. Manufacturer-programmable, reprogrammable
B. Manufacturer-programmable, one-time programmable
C. User-programmable, reprogrammable
D. User-programmable, one-time programmable
Answer: D
Clarification: The fusible-link PROM is user programmable and one time programmable. It means that a written program can not be reprogrammed. EPROMs can be erased and re-programmed.

8. How can ultraviolet erasable PROMs be recognized?
A. There is a small window on the chip
B. They will have a small violet dot next to the #1 pin
C. Their part number always starts with a “U”, such as in U12
D. They are not readily identifiable, since they must always be kept under a small cover
Answer: A
Clarification: An ultraviolet erasable PROMs have small window on the chip with black marked. Such type of PROMS are called EPROMS which are cleared by exposing it to UV radiation. They are re-programmable.

9. Which part of a Flash memory architecture manages all chip functions?
A. Program verify code
B. Floating-gate MOSFET
C. Command code
D. Input/Output pins
Answer: B
Clarification: MOSFET technology is the best one in the manufacturing of chip because it has high flexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory architecture manages all chip functions.

10. How much locations an 8-bit address code can select in memory?
A. 8 locations
B. 256 locations
C. 65,536 locations
D. 131,072 locations
Answer: B
Clarification: An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8 = 256 locations = 2⁸.

11. What is a fusing process?
A. It is a process by which data is passed to the memory
B. It is a process by which data is read through the memory
C. It is a process by which programs are burnout to the diode/transistors
D. It is a process by which data is fetched through the memory
Answer: C
Clarification: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

12. Fusing process is ___________
A. Reversible
B. Irreversible
C. Synchronous
D. Asynchronous
Answer: B
Clarification: Since, any program cannot be reprogrammed in a PROM, so this process is irreversible as PROMs are programmed using the Fusing process. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

13. The cell type used inside a PROM is ___________
A. Link cells
B. Metal cells
C. Fuse cells
D. Electric cells
Answer: C
Clarification: The cell type used inside a PROM is fuse cells by which a program is burnout. Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

14. How many types of fuse technologies are used in PROMs?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs. Three types of fuse technologies are used in PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.

15. Metal links are made up of ___________
A. Polycrystalline
B. Magnesium sulphide
C. Nichrome
D. Silicon dioxide
Answer: C
Clarification: Metal links are made up of Nichrome materials.

Digital Electronic Circuits Interview Questions and Answers for freshers on “Logic Gates and Networks-2”.

1. A single transistor can be used to build which of the following digital logic gates?
A. AND gates
B. OR gates
C. NOT gates
D. NAND gates
Answer: C
Clarification: A transistor can be used as a switch. That is when base is low collector is high (input zero, output one) and base is high collector is low (input 1, output 0).

2. How many truth table entries are necessary for a four-input circuit?
A. 4
B. 8
C. 12
D. 16
Answer: D
Clarification: For 4 inputs: 2⁴ = 16 truth table entries are necessary.

3. Which input values will cause an AND logic gate to produce a HIGH output?
A. At least one input is HIGH
B. At least one input is LOW
C. All inputs are HIGH
D. All inputs are LOW
Answer: C
Clarification: For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will occurs only when all the inputs are high. However, in case of OR gate, if atleast one input is high, the output will be high.

4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
A. OR gates only
B. AND gates and NOT gates
C. AND gates, OR gates, and NOT gates
D. OR gates and NOT gates
Answer: C
Clarification: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for constructing a XOR gate.

5. The basic logic gate whose output is the complement of the input is the ___________
A. OR gate
B. AND gate
C. INVERTER gate
D. XOR gate
Answer: C
Clarification: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and 0 becomes 1.

6. The AND function can be used to ___________ and the OR function can be used to _____________
A. Enable, disable
B. Disable, enable
C. Synchronize, energize
D. Detect, invert
Answer: A
Clarification: The AND gate and OR gate are used for enabling and disabling respectively because of their multiplicity and additivity property. The AND gate outputs 1 when all inputs are at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.

7. The dependency notation “>=1” inside a block stands for which operation?
A. OR
B. XOR
C. AND
D. XNOR
Answer: A
Clarification: The dependency notation “>=1” inside a block stands for OR operation.

8. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
A. LOW
B. HIGH
C. Inverted
D. Floating
Answer: A
Clarification: AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal. Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it outputs 0.

9. Logic gate circuits contain predictable gate functions that open theirs ____________
A. Outputs
B. Inputs
C. Pre-state
D. Impedance state
Answer: B
Clarification: Logic gate circuits contain predictable gate functions that open their inputs because we are free to give any types of inputs.

10. How many NAND circuits are contained in a 7400 NAND IC?
A. 1
B. 2
C. 4
D. 8
Answer: C
Clarification: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated for the NAND operation. Rest 2 pins for power supply.

for interviews,

Digital Electronics/Circuits Multiple Choice Questions on “Procedure for the Design of Combinational Circuits”.

1. The basic building blocks of the arithmetic unit in a digital computers are ____________
A. Subtractors
B. Adders
C. Multiplexer
D. Comparator
Answer: B
Clarification: The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.

2. A digital system consists of _____ types of circuits.
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: A digital system consists of two types of circuits and these are combinational and sequential logic circuit. Combinational circuits are the ones which do not depend on previous inputs while Sequential circuits depend on past inputs.

3. In a combinational circuit, the output at any time depends only on the _______ at that time.
A. Voltage
B. Intermediate values
C. Input values
D. Clock pulses
Answer: C
Clarification: In a combinational circuit, the output at any time depends only on the input values at that time and not on past or intermediate values.

4. In a sequential circuit, the output at any time depends only on the input values at that time.
A. Past output values
B. Intermediate values
C. Both past output and present input
D. Present input values
Answer: C
Clarification: In a sequential circuit, the output at any time depends on the present input values as well as past output values. It also depends on clock pulses depending whether it’s synchronous or asynchronous sequential circuits.

5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different 
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).

A. B, C, D, E, A
B. A, D, E, B, C
C. A, B, E, C, D
D. B, A, E, C, D
Answer: C
Clarification: Combinational circuits are the ones which do not depend on previous inputs and depends only on the present values. The given arrangement in option c is the right sequence for the designing of the combinational circuits.

6. All logic operations can be obtained by means of ____________
A. AND and NAND operations
B. OR and NOR operations
C. OR and NOT operations
D. NAND and NOR operations
Answer: D
Clarification: Since, the logic gates NOR and NAND are known as universal logic gates, therefore it can be used to design all the three basic gates AND, OR and NOT. Thus, it means that any operations can be obtained by implementation of these gates.

7. The design of an ALU is based on ____________
A. Sequential logic
B. Combinational logic
C. Multiplexing
D. De-Multiplexing
Answer: B
Clarification: The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be broken into identical stages connected in cascade through carries.

8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____ result.
A. Input, zero
B. Output, one
C. Input, one
D. Output, zero
Answer: D
Clarification: If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero result.

9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and ___________
A. An underflow condition
B. A neutral condition
C. An overflow condition
D. One indication
Answer: C
Clarification: If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and an overflow condition.

10. The flag bits in an ALU is defined as ____________
A. The total number of registers
B. The status bit conditions
C. The total number of control lines
D. All of the Mentioned
Answer: B
Clarification: In an ALU, status bit conditions are sometimes called condition code bits or flag bits. It is so called because they tend to represent the status of the respect flags after any operation.