300+ REAL TIME Digital Circuits Objective Questions & Answers 2023

250+ TOP MCQs on Arithmetic Operation and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Arithmetic Operation”

1. What is the addition of the binary numbers 11011011010 and 010100101?
A. 0111001000
B. 1100110110
C. 11101111111
D. 10011010011

Answer: C
Clarification: The rules for Binary Addition are :
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 ( Carry 1)

       1
 
   1 1 0 1 1 0 1 1 0 1 0
 
 + 0 0 0 1 0 1 0 0 1 0 1
  _______________________
   1 1 1 0 1 1 1 1 1 1 1
  _______________________

2. Perform binary addition: 101101 + 011011 = ?
A. 011010
B. 1010100
C. 101110
D. 1001000

Answer: D
Clarification:The rules for Binary Addition are :
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 ( Carry 1)

 1 1 1 1 1 1
   1 0 1 1 0 1
 + 0 1 1 0 1 1
 _______________
 1 0 0 1 0 0 0
 _______________

Therefore, the addition of 101101 + 011011 = 1001000.

3. Perform binary subtraction: 101111 – 010101 = ?
A. 100100
B. 010101
C. 011010
D. 011001

Answer: C
Clarification: The rules for Binary Subtraction are :
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

  1 0 1 1 1 1
- 0 1 0 1 0 1
 ____________
  0 1 1 0 1 0
 _____________

Therefore, The subtraction of 101111 – 010101 = 011010.

4. Binary subtraction of 100101 – 011110 is?
A. 000111
B. 111000
C. 010101
D. 101010

Answer: A
Clarification: The rules for Binary Subtraction are :
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

  1 0 0 1 0 1
- 0 1 1 1 1 0
  ___________
  0 0 0 1 1 1
  ___________

Therefore, The subtraction of 100101 – 011110 = 000111.

5. Perform multiplication of the binary numbers: 01001 × 01011 = ?
A. 001100011
B. 110011100
C. 010100110
D. 101010111

Answer: A
Clarification: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

               0 1 0 0 1
             x 0 1 0 1 1
             ____________
               0 1 0 0 1
             0 1 0 0 1 0
           0 0 0 0 0 0 0
         0 1 0 0 1 0 0 0
       0 0 0 0 0 0 0 0 0
      ___________________
       0 0 1 1 0 0 0 1 1
      ___________________

Therefore, 01001 × 01011 = 001100011.

6. 100101 × 0110 = ?
A. 1011001111
B. 0100110011
C. 101111110
D. 0110100101

Answer: C
Clarification: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

                      1 0 0 1 0 1
                 x        0 1 1 0
                       ___________ 
                      0 0 0 0 0 0
                    1 0 0 1 0 1 0
                  1 0 0 1 0 1 0 0
                0 0 0 0 0 0 0 0 0 
               __________________
                0 1 1 0 1 1 1 1 0
              ___________________

Therefore, 100101 x 0110 = 011011110.

7. On multiplication of (10.10) and (01.01), we get ____________
A. 101.0010
B. 0010.101
C. 011.0010
D. 110.0011

Answer: C
Clarification: The rules for binary multiplication are:
0 * 0 = 0
0 * 1 = 0
1 * 0 = 0
1 * 1 = 1

           1 0.1 0
      x    0 1.0 1
         __________
            1 0 1 0
          0 0 0 0 0
        1 0 1 0 0 0
      0 0 0 0 0 0 0
     _______________
      0 1 1.0 0 1 0
     _________________

Therefore, 10.10 x 01.01 = 011.0010.

8. Divide the binary numbers: 111101 ÷ 1001 and find the remainder.
A. 0010
B. 1010
C. 1100
D. 0111

Answer: D
Clarification: Binary Division is accomplished using long division method.

1 0 0 1 ) 1 1 1 1 0 1 ( 1 1
          1 0 0 1
          __________
          0 1 1 0 0
            1 0 0 1
          ___________
            0 1 1 1

Therefore, the remainder of 111101 ÷ 1001 = 0111.

9. Divide the binary number (011010000) by (0101) and find the quotient.
A. 100011
B. 101001
C. 110010
D. 010001

Answer: B
Clarification:

0 1 0 1 ) 0 1 1 0 1 0 0 0 0 ( 0 1 0 1 1 1
          0 0 0 0
         _____________________
          0 1 1 0 1 
          0 0 1 0 1
         ______________
          0 1 0 0 0 0
          0 0 0 0 0 0
          ______________________
              1 0 0 0 0
	      0 0 1 0 1			
           ____________________
		0 1 0 1 1 0
		0 0 0 1 0 1 
 	     ____________________
		  1 0 0 0 1 0 
		  0 0 0 1 0 1 
	   ________________________
	            1 1 1 0 1 0 
	            0 0 0 1 0 1
 	    ________________________
			1 0 1 0 1
			0 0 1 0 1 
 	     ________________________
		        1 0 0 0 0

Therefore, the quotient of 011010000 ÷ 1001 = 101001.

10. Binary subtraction of 101101 – 001011 = ?
A. 100010
B. 010110
C. 110101
D. 101100

Answer: A
Clarification: The rules for binary subtraction are:
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

  1 0 1 1 0 1
- 0 0 1 0 1 1
  ____________
  1 0 0 0 1 0
  ____________

Therefore, the subtraction of 101101 – 001011 = 100010.

250+ TOP MCQs on Emitter-Coupled Logic(ECL) and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Emitter-Coupled Logic(ECL)”.

1. The full form of ECL is __________
A. Emitter-collector logic
B. Emitter-complementary logic
C. Emitter-coupled logic
D. Emitter-cored logic
Answer: C
Clarification: The full form of ECL is emitter-coupled logic.

2. Which logic is the fastest of all the logic families?
A. TTL
B. ECL
C. HTL
D. DTL
Answer: B
Clarification: ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results in the highest transmission rate.

3. The full form of CML is __________
A. Complementary mode logic
B. Current mode logic
C. Collector mode logic
D. Collector Mixed Logic
Answer: C
Clarification: The full form of CML is Collector Mode Logic.

4. Sometimes ECL can also be named as __________
A. EEL
B. CEL
C. CML
D. CCL
Answer: C
Clarification: ECL (Emitter Coupled LogiC. can also be named as CML(Collector Mode LogiC..

5. In an ECL the output is taken from __________
A. Emitter
B. Base
C. Collector
D. Junction of emitter and base
Answer: C
Clarification: Though, the emitter and collector of the ECL are coupled together. So, the output will be taken from a collector.

6. The ECL behaves as __________
A. NOT gate
B. NOR gate
C. NAND gate
D. AND gate
Answer: B
Clarification: The ECL behaves as NOR gate because if any of the input voltages go high as compared to the reference voltage, the output is low and the output is high only when all the input voltages are low.

7. In ECL the fanout capability is __________
A. High
B. Low
C. Zero
D. Sometimes high and sometimes low
Answer: A
Clarification: If the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of inputs that a single gate output can accept.

8. ECL’s major disadvantage is that __________
A. It requires more power
B. It’s fanout capability is high
C. It creates more noise
D. It is slow
Answer: A
Clarification: ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families. But ECL logic gates have clock frequency. Thus, they have a fast operation.

9. The full form of SCFL is __________
A. Source-collector logic
B. Source-coupled logic
C. Source-complementary logic
D. Source Cored Logic
Answer: B
Clarification: The full form of SCFL is source-coupled logic.

10. The equivalent of emitter-coupled logic made out of FETs is called __________
A. CML
B. SCFL
C. FECL
D. EFCL
Answer: B
Clarification: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL). Like ECL, SCL is also the fastest among the logic families.

11. ECL was invented in _______ by __________
A. 1956, Baker clamp
B. 1976, James R. Biard
C. 1956, Hannon S. Yourke
D. 1976, Yourke
Answer: C
Clarification: ECL was invented in August 1956 at IBM by Hannon S Yourke.

12. At the time of invention, an ECL was called as __________
A. Source-coupled logic
B. Current Mode Logic
C. Current-steering logic
D. Emitter-coupled logic
Answer: C
Clarification: At the time of invention, an ECL was called a current-steering logic because it involved current switching.

13. The ECL circuits usually operates with __________
A. Negative voltage
B. Positive voltage
C. Grounded voltage
D. High Voltage
Answer: A
Clarification: The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to grounD., in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.

14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
A. ECL
B. VECL
C. PECL
D. LECL
Answer: C
Clarification: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V instead of 5 V supply.

250+ TOP MCQs on BCD Adder and Answers

Digital Electronics/Circuits Multiple Choice Questions on “BCD Adder”.

1. The decimal number system represents the decimal number in the form of ____________
A. Hexadecimal
B. Binary coded
C. Octal
D. Decimal
Answer: B
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Hexadecimal and Octal are number systems having base 16 and 8 respectively.

2. 2⁹ input circuit will have total of ____________
A. 32 entries
B. 128 entries
C. 256 entries
D. 512 entries
Answer: D
Clarification: 2⁹ input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

3. BCD adder can be constructed with 3 IC packages each of ____________
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Answer: C
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.

4. The output sum of two decimal digits can be represented in ____________
A. Gray Code
B. Excess-3
C. BCD
D. Hexadecimal
Answer: C
Clarification: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.

5. The addition of two decimal digits in BCD can be done through ____________
A. BCD adder
B. Full adder
C. Ripple carry adder
D. Carry look ahead
Answer: A
Clarification: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in addition by the user converted into binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.

6. 3 bits full adder contains ____________
A. 3 combinational inputs
B. 4 combinational inputs
C. 6 combinational inputs
D. 8 combinational inputs
Answer: D
Clarification: 3 bits full adder contains 2³ = 8 combinational inputs.

7. The simplified expression of full adder carry is ____________
A. c = xy+xz+yz
B. c = xy+xz
C. c = xy+yz
D. c = x+y+z
Answer: A
Clarification: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.

8. Complement of F’ gives back __________
A. F’
B. F
C. FF
D. FF’
Answer: B
Clarification: Complement means inversion. So, complement of F’ gives back F, as per the Law of Involution.

9. Decimal digit in BCD can be represented by ____________
A. 1 input line
B. 2 input lines
C. 3 input lines
D. 4 input lines
Answer: D
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.

10. The number of logic gates and the way of their interconnections can be classified as ____________
A. Logical network
B. System network
C. Circuit network
D. Gate network
Answer: A
Clarification: The number of different levels of logic gates is represented in a fashion which is known as a logical network.

250+ TOP MCQs on D Flip Flop and Answers

Digital Electronics/Circuits Multiple Choice Questions on “D Flip Flop”.

1. In D flip-flop, D stands for _____________
A. Distant
B. Data
C. Desired
D. Delay
Answer: B
Clarification: The D of D-flip-flop stands for “data”. It stores the value on the data line.

2. The D flip-flop has _______ input.
A. 1
B. 2
C. 3
D. 4
Answer: A
Clarification: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

3. The D flip-flop has ______ output/outputs.
A. 2
B. 3
C. 4
D. 1
Answer: A
Clarification: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

4. A D flip-flop can be constructed from an ______ flip-flop.
A. S-R
B. J-K
C. T
D. S-K
Answer: A
Clarification: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.

5. In D flip-flop, if clock input is LOW, the D input ___________
A. Has no effect
B. Goes high
C. Goes low
D. Has effect
Answer: A
Clarification: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.

6. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
A. 0
B. 1
C. Forbidden
D. Toggle
Answer: A
Clarification: If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram:

7. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?
A. The logic level at the D input is transferred to Q on NGT of CLK
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH
C. The Q output is ALWAYS identical to the D input when CLK = PGT
D. The Q output is ALWAYS identical to the D input
Answer: A
Clarification: By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

8. Which of the following is correct for a gated D flip-flop?
A. The output toggles if one of the inputs is held HIGH
B. Only one of the inputs can be HIGH at a time
C. The output complement follows the input when enabled
D. Q output follows the input D when the enable is HIGH
Answer: D
Clarification: If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the value on the data line.

9. With regard to a D latch ________
A. The Q output follows the D input when EN is LOW
B. The Q output is opposite the D input when EN is LOW
C. The Q output follows the D input when EN is HIGH
D. The Q output is HIGH regardless of EN’s input state
Answer: C
Clarification: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input. It stores the value on the data line.

10. Which of the following is correct for a D latch?
A. The output toggles if one of the inputs is held HIGH
B. Q output follows the input D when the enable is HIGH
C. Only one of the inputs can be HIGH at a time
D. The output complement follows the input when enabled
Answer: B
Clarification: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. It stores the value on the data line.

11. Which of the following describes the operation of a positive edge-triggered D flip-flop?
A. If both inputs are HIGH, the output will toggle
B. The output will follow the input on the leading edge of the clock
C. When both inputs are LOW, an invalid state exists
D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Answer: B
Clarification: Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.

12. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
A. CLK = NGT, D = 0
B. CLK = PGT, D = 0
C. CLOCK NGT, D = 1
D. CLOCK PGT, D = 1
Answer: D
Clarification: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.

13. A positive edge-triggered D flip-flop will store a 1 when ________
A. The D input is HIGH and the clock transitions from HIGH to LOW
B. The D input is HIGH and the clock transitions from LOW to HIGH
C. The D input is HIGH and the clock is LOW
D. The D input is HIGH and the clock is HIGH
Answer: B
Clarification: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.

14. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
A. Due to its capability to receive data from flip-flop
B. Due to its capability to store data in flip-flop
C. Due to its capability to transfer the data into flip-flop
D. Due to erasing the data from the flip-flop
Answer: C
Clarification: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.

15. The characteristic equation of D-flip-flop implies that ___________
A. The next state is dependent on previous state
B. The next state is dependent on present state
C. The next state is independent of previous state
D. The next state is independent of present state
Answer: D
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is independent of the present state.

Digital Electronics/Circuits Multiple Choice Questions on “Introduction of Memory Devices – 1”.

1. Memory is a/an ___________
A. Device to collect data from other computer
B. Block of data to keep data separately
C. Indispensable part of computer
D. Device to connect through all over the world
Answer: C
Clarification: Memory is an indispensable unit of a computer and microprocessor based systems which stores permanent or temporary data.

2. The instruction used in a program for executing them is stored in the __________
A. CPU
B. Control Unit
C. Memory
D. Microprocessor
Answer: C
Clarification: All of the program and the instructions are stored in the memory. The processor fetches it as and when required.

3. A flip flop stores __________
A. 10 bit of information
B. 1 bit of information
C. 2 bit of information
D. 3-bit information
Answer: B
Clarification: A flip-flop has capability to store 1 bit of information. It can be used further after erasing previous information.

4. A register is able to hold __________
A. Data
B. Word
C. Nibble
D. Both data and word
Answer: B
Clarification: Register is also a part of memory inside a computer. It stands there to hold a word. A word is a group of 16-bits or 2-bytes.

5. A register file holds __________
A. A large number of word of information
B. A small number of word of information
C. A large number of programs
D. A modest number of words of information
Answer: D
Clarification: A register file is different from a simple register because of capability to hold a modest number of words of information. A word is a group of 16-bits or 2-bytes.

6. The very first computer memory consisted of __________
A. A small display
B. A large memory storage equipment
C. An automatic keyboard input
D. An automatic mouse input
Answer: B
Clarification: The very first computer memory consisted of a minute magnetic toroid, which required large, bulky circuit boards stored in large cabinates.

7. A minute magnetic toroid is also called as __________
A. Large memory
B. Small memory
C. Core memory
D. Both small and large memory
Answer: C
Clarification: A minute magnetic toroid is also called as core memory which is made up of a semiconductor. A semiconductor is a device whose electrical conductivity lies between that of conductor and insulator.

8. Which one of the following has capability to store data in extremely high densities?
A. Register
B. Capacitor
C. Semiconductor
D. Flip-Flop
Answer: C
Clarification: Semiconductor has capability to store data in extremely high densities.

9. A large memory is compressed into a small one by using __________
A. LSI semiconductor
B. VLSI semiconductor
C. CDR semiconductor
D. SSI semiconductor
Answer: B
Clarification: VLSI (Very Large Scale Integration) semiconductor is used in modern computers to short the size of memory.

10. VLSI chip utilizes __________
A. NMOS
B. CMOS
C. BJT
D. All of the Mentioned
Answer: D
Clarification: VLSI (Very Large Scale Integration) is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS. It can include 10,000 to 100,000 gates per IC.

11. CD-ROM refers to __________
A. Floppy disk
B. Compact Disk-Read Only Memory
C. Compressed Disk-Read Only Memory
D. Compressed Disk- Random Access Memory
Answer: B
Clarification: CD-ROM refers to Compact Disk-Read Only Memory.

12. Data stored in an electronic memory cell can be accessed at random and on demand using __________
A. Memory addressing
B. Direct addressing
C. Indirect addressing
D. Control Unit
Answer: B
Clarification: Direct addressing eliminates the need to process a large stream of irrelevant data in order to the desired data word.

13. The full form of PLD is __________
A. Programmable Large Device
B. Programmable Long Device
C. Programmable Logic Device
D. Programmable Lengthy Device
Answer: C
Clarification: The full form of PLD is Programmable Logic Device.

14. The evolution of PLD began with __________
A. EROM
B. RAM
C. PROM
D. EEPROM
Answer: A
Clarification: The evolution of PLD (Programmable Logic Device) began with Programmable Read Only Memory (i.e. PROM). Here, the ROM can be externally programmed as per the user.

15. A ROM is defined as __________
A. Read Out Memory
B. Read Once Memory
C. Read Only Memory
D. Read One Memory
Answer: C
Clarification: A ROM is defined as Read Only Memory which can read the instruction stored in a computer.

Category: Digital Circuits Objective Questions

250+ TOP MCQs on Arithmetic Operation and Answers

250+ TOP MCQs on Emitter-Coupled Logic(ECL) and Answers

250+ TOP MCQs on BCD Adder and Answers

250+ TOP MCQs on D Flip Flop and Answers

250+ TOP MCQs on Introduction of Memory Devices – 1 and Answers

250+ TOP MCQs on 1’s, 2’s, 9’s & 10’s Complements – 1 and Answers