Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “Integrated-injection Logic(I^2L)”.

1. The full form of IIL is __________
A. Injection integrated logic
B. Integrated inspected logic
C. Integrated injection logic
D. Injection Inspected Logic
Answer: C
Clarification: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction transistors and had a speed comparable to TTl and power consumption equivalent to CMOS.

2. Integrated injection logic is a class of digital circuits built with __________
A. Single collector BJT
B. Double emitter BJT
C. Multiple emitter BJT
D. Multiple collector BJT
Answer: D
Clarification: Integrated injection logic is a class of digital circuits built with multiple collector bipolar junction transistors (BJT).

3. IIL has _____ noise immunity.
A. High
B. Low
C. Neutral
D. Nil
Answer: A
Clarification: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction transistors and had speed comparable to TTl and power consumption equivalent to CMOS. IIL has high noise immunity because it operates by current instead of voltage.

4. IIL is sometimes also known as __________
A. Single transistor logic
B. Multiple transistor logic
C. Merged transistor logic
D. Mixed Transistor Logic
Answer: C
Clarification: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction transistors and had speed comparable to TTl and power consumption equivalent to CMOS. IIL is sometimes also known as merged transistor logic.

5. Integrated Injection logic cannot be denoted as __________
A. IIL
B. I2L
C. I^2L
D. I TWO L
Answer: D
Clarification: The full form of IIL is Integrated injection logic. It is made up of multiple bipolar junction transistors and had speed comparable to TTl and power consumption equivalent to CMOS. Integrated Injection logic can be denoted as IIL, I^2L and I2L as well.

6. The heart of an I2L circuit is the __________
A. Common collector open emitter inverter
B. Common emitter open collector inverter
C. Open emitter common collector inverter
D. Open Emitter Open Collector Inverter
Answer: B
Clarification: The heart of an I2L circuit is the common emitter open collector inverter. The emitter is connected to the ground, with the base having an input behaving as either current sink or high impedance floating condition. The output of an inverter is connected to the collector.

7. In Integrated Injection, logic input is supplied to the __________
A. Emitter
B. Base
C. Collector
D. Collector Emitter
Answer: B
Clarification: In IIL, the input is supplied to the base as either a current sink (low logic level) or as a high impedance floating condition (high logic level). The output of an inverter is connected to the collector.

8. In Integrated Injection, logic output is received through the __________
A. Emitter
B. Base
C. Collector
D. Base Emitter Junction
Answer: C
Clarification: In Integrated Injection logic output is received through the collector. The output of an inverter is connected at the collector.

9. When the outputs of two inverters are wired together the result is __________
A. A two-input NOR gate
B. A single-input NOR gate
C. A two-input NAND gate
D. A single-input NAND gate
Answer: A
Clarification: When the outputs of two inverters are wired together then the result is a two-input NOR gate because the configuration (NOT A. AND (NOT B. is equivalent to NOT (A OR B.. In a NOR gate, the output is high only when all of its input are at logic 0 else, the output is low.

10. IIL was commonly used before the advent of CMOS logic by company ___________
A. Samsung
B. Nokia
C. Motorola
D. Apple
Answer: C
Clarification: I2L is relatively simple to construct on an integrated circuit and was commonly used before the advent of CMOS logic by companies such as Motorola.

11. Which company introduced one of the first consumer-grade digital watches (the Black Watch) which used I2L technology?
A. Cambridge Consultants Pvt Ltd
B. Sinclair Radionics Ltd
C. National Research and Development Council
D. Westminster
Answer: B
Clarification: Sinclair Radionics Ltd introduced one of the first consumer-grade digital watches (the Black Watch) in August 1975, which used I2L technology.

Digital Electronics/Circuits Multiple Choice Questions on “Combinational Circuits”.

1. Which of the circuits in figure (a to D. is the sum-of-products implementation of figure (e)?

A. a
B. b
C. c
D. d
Answer: D
Clarification: SOP means Sum Of Products form which represents the sum of product terms having variables in complemented as well as in uncomplemented form. Here, the diagram of d contains the OR gate followed by the AND gates, so it is in SOP form.

2. Which of the following logic expressions represents the logic diagram shown?

A. X=AB’+A’B
B. X=(AB.’+AB
C. X=(AB.’+A’B’
D. X=A’B’+AB
Answer: D
Clarification: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB. = AB + A’B’.

3. The device shown here is most likely a ________

A. Comparator
B. Multiplexer
C. Inverter
D. Demultiplexer
Answer: D
Clarification: The given diagram is demultiplexer, because it takes single input & gives many outputs. A demultiplexer is a combinational circuit that takes a single output and latches it to multiple outputs depending on the select lines.

4. What type of logic circuit is represented by the figure shown below?

A. XOR
B. XNOR
C. AND
D. XAND
Answer: B
Clarification: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.

5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?

A. d
B. a
C. c
D. b
Answer: A
Clarification: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
0 0 1
0 1 0
1 0 0
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.

6. Which of the following combinations of logic gates can decode binary 1101?
A. One 4-input AND gate
B. One 4-input AND gate, one inverter
C. One 4-input AND gate, one OR gate
D. One 4-input NAND gate, one inverter
Answer: B
Clarification: For decoding any number output must be high for that code and this is possible in One 4-input NAND gate, one inverter option only. A decoder is a combinational circuit that converts binary data to n-coded data upto 2ⁿ outputs.

7. What is the indication of a short to ground in the output of a driving gate?
A. Only the output of the defective gate is affected
B. There is a signal loss to all load gates
C. The node may be stuck in either the HIGH or the LOW state
D. The affected node will be stuck in the HIGH state
Answer: B
Clarification: Short to ground in the output of a driving gate indicates of a signal loss to all load gates. This results in information being disrupted and loss of data.

8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs?

A. All are HIGH
B. All are LOW
C. All but Y0 are LOW
D. All but Y0 are HIGH
Answer: D
Clarification: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.

9. The carry propagation can be expressed as ________
A. Cp = AB
B. Cp = A + B
C. All but Y0 are LOW
D. All but Y0 are HIGH
Answer: B
Clarification: This happens in parallel adders (where we try to add numbers in parallel via more than one adders). A carry propagation occurs when carry from one adder needs to be forwarded to other adder and that second adder is holding the computation (addition) because carry from first adder has not come yet. So, there is a slight delay for second adder and this is known as carry propagation.

10. 3 bits full adder contains ________
A. 3 combinational inputs
B. 4 combinational inputs
C. 6 combinational inputs
D. 8 combinational inputs
Answer: D
Clarification: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM. Three bits full adder requires 2³ = 8 combinational circuits.

Digital Electronics/Circuits Multiple Choice Questions on “Triggering of Flip Flops”.

1. The characteristic equation of J-K flip-flop is ______________
A. Q(n+1)=JQ(n)+K’Q(n)
B. Q(n+1)=J’Q(n)+KQ'(n)
C. Q(n+1)=JQ'(n)+KQ(n)
D. Q(n+1)=JQ'(n)+K’Q(n)
Answer: D
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).

2. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer: C
Clarification: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

3. In J-K flip-flop, the function K=J is used to realize _____________
A. D flip-flop
B. S-R flip-flop
C. T flip-flop
D. S-K flip-flop
Answer: C
Clarification: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

4. The only difference between a combinational circuit and a flip-flop is that _____________
A. The flip-flop requires previous state
B. The flip-flop requires next state
C. The flip-flop requires a clock pulse
D. The flip-flop depends on the past as well as present states
Answer: C
Clarification: Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as well as present states. Whereas, in case of combinational circuits, they only depend on the present state.

5. How many stable states combinational circuits have?
A. 3
B. 4
C. 2
D. 5
Answer: C
Clarification: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional state known as Forbidden State.

6. The flip-flop is only activated by _____________
A. Positive edge trigger
B. Negative edge trigger
C. Either positive or Negative edge trigger
D. Sinusoidal trigger
Answer: C
Clarification: Flip flops can be activated with either a positive or negative edge trigger.

7. The S-R latch composed of NAND gates is called an active low circuit because _____________
A. It is only activated by a positive level trigger
B. It is only activated by a negative level trigger
C. It is only activated by either a positive or negative level trigger
D. It is only activated by sinusoidal trigger
Answer: B
Clarification: Active low indicates that only an input value of 0 sets or resets the circuit.

8. Both the J-K & the T flip-flop are derived from the basic _____________
A. S-R flip-flop
B. S-R latch
C. D latch
D. D flip-flop
Answer: B
Clarification: The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A latch is similar to a flip-flop, only without a clock input.

9. The flip-flops which has not any invalid states are _____________
A. S-R, J-K, D
B. S-R, J-K, T
C. J-K, D, S-R
D. J-K, D, T
Answer: D
Clarification: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or forbidden state where no output could be determined.

10. What does the triangle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Edge triggered
C. Both Level enabled & Edge triggered
D. Level triggered
Answer: B
Clarification: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.

11. What does the circle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: C
Clarification: The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.

12. What does the direct line on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: D
Clarification: The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.

13. What does the half circle on the clock input of a J-K flip-flop mean?
A. Level enabled
B. Positive edge triggered
C. negative edge triggered
D. Level triggered
Answer: D
Clarification: The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.

14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is _____________
A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer: D
Clarification: As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.

15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
A. The clock pulse is LOW
B. The clock pulse is HIGH
C. The clock pulse transitions from LOW to HIGH
D. The clock pulse transitions from HIGH to LOW
Answer: C
Clarification: Edge triggered device will follow the input condition when there is a transition. It is said to be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be a negative edge triggered when a transition occurs from HIGH to LOW.

Digital Electronic/Circuits assessment questions on “Introduction of Memory Devices-2”.

1. The full form of ROM is __________
A. Read Outside Memory
B. Read Out Memory
C. Read Only Memory
D. Read One Memory
Answer: C
Clarification: The full form of ROM is Read Only Memory.

2. ROM consist of __________
A. NOR and OR arrays
B. NAND and NOR arrays
C. NAND and OR arrays
D. NOR and AND arrays
Answer: C
Clarification: ROM consists of NAND and OR arrays which can be programmed by the user to implement combinational & sequential functions. Combinational Operations like that of adders and subtractors and Sequential Functions like that of storing in the memory.

3. For reprogrammability, PLDs use __________
A. PROM
B. EPROM
C. CDROM
D. PLA
Answer: B
Clarification: For reprogrammability, PLDs use EPROM (i.e. Erasable PROM). It erases the previous program and starts uploading a new one. However, data is erased by exposing it to UV-light, which is a tedious and time-consuming process.

4. The full form of PROM is __________
A. Previous Read Only Memory
B. Programmable Read Out Memory
C. Programmable Read Only Memory
D. Previous Read Out Memory
Answer: C
Clarification: The full form of PROM is Programmable Read Only Memory, where the ROM can be programmed by the user.

5. The full form of EPROM is __________
A. Easy Programmable Read Only Memory
B. Erasable Programmable Read Only Memory
C. Eradicate Programmable Read Only Memory
D. Easy Programmable Read Out Memory
Answer: B
Clarification: The full form of EPROM is Erasable Programmable Read Only Memory, where the ROM can be erased and re-used by the user.

6. PLDs with programmable AND and fixed OR arrays are called __________
A. PAL
B. PLA
C. APL
D. PPL
Answer: A
Clarification: PLDs with programmable AND and fixed OR arrays are called PAL (i.e. Programmable Array LogiC.. However, PAL is less flexible but has higher speed.

7. When both the AND and OR are programmable, such PLDs are known as __________
A. PAL
B. PPL
C. PLA
D. APL
Answer: C
Clarification: When both the AND and OR are programmable, such PLDs are known as PLA (i.e. Programmable Logic Array). However, PLA is more flexible but has less speed.

8. ASIC stands for __________
A. Application Special Integrated Circuits
B. Applied Special Integrated Circuits
C. Application Specific Integrated Circuits
D. Applied Specific Integrated Circuits
Answer: C
Clarification: In digital electronics, ASIC stands for Application Specific Integrated Circuits. It is a customized integrated circuit which is produced for a specific use and not for a common-purpose.

9. The programmability and high density of PLDs make them useful in the design of __________
A. ISAC
B. ASIC
C. SACC
D. CISF
Answer: B
Clarification: The programmability and high density of PLDs make them useful in the design of ASIC (i.e. Application Specific Integrated Circuits) where design changes can be more rapidly and inexpensively.

10. FPGA stands for __________
A. Full Programmable Gate Array
B. Full Programmable Genuine Array
C. First Programmable Gate Array
D. Field Programmable Gate Array
Answer: D
Clarification: In digital electronics, FPGA stands for Field Programmable Gate Array. This type of integrated circuit is for general-purpose which is configured by the user as per their requirement.

11. Which of the following is a reprogrammable gate array?
A. EPROM
B. FPGA
C. Both EPROM and FPGA
D. ROM
Answer: C
Clarification: Both FPGA and EPROM are reprogrammable gate array.

12. The difference between FPGA and PLD is that __________
A. FPGA is slower than PLD
B. FPGA has high power dissipation
C. FPGA incorporates logic blocks
D. All of the Mentioned
Answer: C
Clarification: The difference between FPGA and PLD is that FPGA incorporates logic blocks instead of fixed AND-OR gates and is faster with low power dissipation. FPGAs are designed for having higher gate count whereas, PLDs are used for lesser gate counts.

assessment questions on all areas of Digital Electronic Circuits,

Digital Electronic Circuits Interview Questions and Answers on “1’s,2’s,9’s & 10’s Complements-2”.

1. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in _________
A. Successor
B. Overflow
C. Underflow
D. Predecessor
Answer: B
Clarification: If the number of bits in the sum exceeds the number of bits in each added numbers, it results in overflow and is also known as excess-one. In case of any arithmetic operation, if the result has less number of bits than the operands, then it is known as underflow condition.

2. An overflow is a _________
A. Hardware problem
B. Software problem
C. User input problem
D. Input Output Error
Answer: B
Clarification: An overflow is a software problem which occurs when the processor cannot handle the result properly when it produces an out of the range output.

3. An overflow occurs in _________
A. MSD position
B. LSD position
C. Middle position
D. Signed Bit
Answer: A
Clarification: An overflow occurs at the Most Significant Digit position. It occurs when the processor cannot handle the result properly when it produces an out of the range output.

4. Logic circuitry is used to detect _________
A. Underflow
B. MSD
C. Overflow
D. LSD
Answer: C
Clarification: To check the overflow logic circuitry is used in each case. Overflow occurs when the processor cannot handle the result properly when it produces an out of the range output.

5. 1’s complement can be easily obtained by using _________
A. Comparator
B. Inverter
C. Adder
D. Subtractor
Answer: B
Clarification: With the help of inverter the 1’s complement is easily obtained. Since, during the operation of 1’s complement 1 is converted into 0 and vice-versa and this is well suited for the inverter.

6. The advantage of 2’s complement system is that _________
A. Only one arithmetic operation is required
B. Two arithmetic operations are required
C. No arithmetic operations are required
D. Different Arithmetic operations are required
Answer: A
Clarification: The advantage of 2’s complement is that only one arithmetic operation is required for 2’s complement’s operation and that is only addition. Just by adding a 1 bit to 1’s complement, we get 2’s complement.

7. The 1’s complements requires _________
A. One operation
B. Two operations
C. Three operations
D. Combined Operations
Answer: A
Clarification: Only one operation is required for 1’s complement operation. This includes only inversion of 1’s to 0’s and 0’s to 1’s.

8. Which one is used for logical manipulations?
A. 2’s complement
B. 9’s complement
C. 1’s complement
D. 10’s complement
Answer: C
Clarification: For logical manipulations, 1’s complement is used, as all logical operations take place with binary numbers.

9. For arithmetic operations only _________
A. 1’s complement is used
B. 2’s complement
C. 10’s complement
D. 9’s complement
Answer: B
Clarification: Only 2’s complement is used for arithmetic operations, as it is more fast.

10. The addition of +19 and +43 results as _________ in 2’s complement system.
A. 11001010
B. 101011010
C. 00101010
D. 0111110
Answer: D
Clarification: The decimal numbers are converted to their respective binary equivalent and then the binary addition rules are applied.

for Interviews,

Digital Electronics/Circuits Multiple Choice Questions on “MOS Digital Integrated Circuits”.

1. The full form of MOS is ___________
A. Metal oxide semiconductor
B. Metal oxygen semiconductor
C. Metallic oxide semiconductor
D. Metallic oxygen semiconductor
Answer: A
Clarification: The full form of MOS is “Metal Oxide Semiconductor”. It is a type of transistor having 3 layers: a metal conductor, an insulating silicon layer and a semiconductor silicon layer.

2. What are the types of MOSFET devices available?
A. P-type enhancement type MOSFET
B. N-type enhancement type MOSFET
C. Depletion type MOSFET
D. All of the mentioned
Answer: D
Clarification: MOSFET are of two types: enhancement and depletion type. Further, these are classified into n-type and p-type device. The depletion type is switched on without the application of gate bias voltage and the enhancement type is switched on with the application of gate voltage.

3. Which insulating layer used in the fabrication of MOSFET?
A. Aluminium oxide
B. Silicon Nitride
C. Silicon dioxide
D. Aluminium Nitrate
Answer: C
Clarification: Silicon dioxide is used as an insulating layer in the fabrication of MOSFET. It gives an extremely high input resistance in the order of 10¹⁰ to 10¹⁵ Ω for MOSFET.

4. Which of the following plays an important role in improving the device performance of MOSFET?
A. Dielectric constant
B. Threshold voltage
C. Power supply voltage
D. Gate to drain voltage
Answer: B
Clarification: In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not compatible with the supply of 5V which is used in digital ICs. So, for the improvement of the device’s performance the magnitude of threshold voltage should be reduced.

5. A technique used to reduce the magnitude of threshold voltage of MOSFET is the ___________
A. Use of complementary MOSFET
B. Use of Silicon nitride
C. Using thin film technology
D. Increasing potential of the channel
Answer: B
Clarification: Silicon nitride is sandwiched between two SiO2 layer and provide necessary barrier. The dielectric constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in overall dielectric constant reduces threshold voltage.

6. What is used to higher the speed of operation in MOSFET fabrication?
A. Ceramic gate
B. Silicon dioxide
C. Silicon nitride
D. Poly silicon gate
Answer: D
Clarification: In conventional metal gate small overlap capacitance is present, which lowers the speed of operation. With the presence of self aligning property of the poly silicon gate it eliminates this capacitance. Using a process called ion-implantation, polysilicon, the drain and the source get doped. However, the thin oxide under silicon gate acting as a mask for the process and thus develops the gate aligning property.

7. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?

Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to include 
source, gate and drain.
Step 2: The contact areas are defined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called field oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.

A. 1->5->3->4->2->6
B. 1->3->4->2->5->6
C. 1->5->4->3->2->6
D. 1->4->2->5->3->6
Answer: A
Clarification: These steps are the sequence of steps involved in fabrication of poly silicon gate MOSFET. With the help of poly silicon gate doping, it highers the speed of operation of the MOSFET.

8. Why MOSFET is preferred over BJT in IC components?
A. MOSFET has low packing density
B. MOSFET has medium packing density
C. MOSFET has high packing density
D. MOSFET has no packing density
Answer: A
Clarification: MOSFET is preferred over BJT because of its low packaging density. Thus, more number of MOSFET memory cells can be accommodated in a particular area as compared to BJT.

9. Critical defects per unit chip area are ________ for a MOS transistor.
A. High
B. Low
C. Neutral
D. Very High
Answer: B
Clarification: Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps in the fabrication of a MOS transistor. Also, MOSFET has low packaging density.

10. MOS is being used in ___________
A. LSI
B. VLSI
C. MSI
D. Both LSI and VLSI
Answer: D
Clarification: Since more transistor and circuitry functions can be achieved on a single chip with MOS technology that is why MOS is being used in LSI and VLSI. LSI stands for Large Scale Integration and VLSI stands for Very Large Scale Integration.