Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “Universal Shift Registers”.

1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A. Ring shift
B. Clock
C. Johnson
D. Binary
Answer: A
Clarification: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. Thus, it generates equally spaced timing pulses.

2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________
A. 1101
B. 0111
C. 0001
D. 1110
Answer: B
Clarification: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011 and remained bit in register is 1. Therefore, 0111 is the required solution.
1011 | 1101
101 | 1110 -> 1^st clock pulse
10 | 1111 -> 2^nd clock pulse
1 | 0111 -> 3^rd clock pulse.

3. To operate correctly, starting a ring shift counter requires __________
A. Clearing all the flip-flops
B. Presetting one flip-flop and clearing all others
C. Clearing one flip-flop and presetting all others
D. Presetting all the flip-flops
Answer: B
Clarification: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input. To operate correctly, starting a ring shift counter requires presetting one flip-flop and clearing all others so that it can shift to the next bit.

4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.
A. Right, one
B. Right, two
C. Left, one
D. Left, three
Answer: A
Clarification: If register shifts towards left then it shift by a bit to the left and if register shifts right then it shift to the right by one bit. Since, it receives parallel data, then by default, it will shift to right by one position.

5. How many clock pulses will be required to completely load serially a 5-bit shift register?
A. 2
B. 3
C. 4
D. 5
Answer: D
Clarification: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift register. So, for 5-bit shift register we would require of 5 clock pulses.

6. How is a strobe signal used when serially loading a shift register?
A. To turn the register on and off
B. To control the number of clocks
C. To determine which output Qs are used
D. To determine the FFs that will be used
Answer: B
Clarification: A strobe is used to validate the availability of data on the data line. It (an auxiliary signal used to help synchronize the real data in an electrical bus when the bus components have no common clock) signal is used to control the number of clocks during serially loading a shift register.

7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
A. 1.67 s
B. 26.67 s
C. 26.7 ms
D. 267 ms
Answer: B
Clarification: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.

8. What are the three output conditions of a three-state buffer?
A. HIGH, LOW, float
B. High-Z, 0, float
C. Negative, positive, 0
D. 1, Low-Z, float
Answer: A
Clarification: Three conditions of a three-state buffer are HIGH, LOW & float.

9. The primary purpose of a three-state buffer is usually ____________
A. To provide isolation between the input device and the data bus
B. To provide the sink or source current required by any device connected to its output without loading down the output device
C. Temporary data storage
D. To control data flow
Answer: A
Clarification: The primary purpose of a three-state buffer is usually to provide isolation between the input device or peripheral devices and the data bus. Three conditions of a three-state buffer are HIGH, LOW & float.

10. What is the difference between a ring shift counter and a Johnson shift counter?
A. There is no difference
B. A ring is faster
C. The feedback is reversed
D. The Johnson is faster
Answer: C
Clarification: A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Whereas, a Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage.

tough Digital Electronic/Circuits questions and answers on “Random Access Memory-3”.

1. Dynamic RAM is more preferable than static RAM, why?
A. DRAM is of the lowest cost, lowest density
B. DRAM is of the highest cost, reduced size
C. DRAM is of the lowest cost, highest density
D. DRAM is more flexible and lowest storage capacity
Answer: C
Clarification: The Dynamic Random Access Memory is the lowest cost, highest density random access memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more compared to SRAM.

2. The memory size of DRAM is ____________
A. 1 to 100 MB
B. 512 to 1024 MB
C. 64 to 512 MB
D. 16 to 256 MB
Answer: D
Clarification: The Dynamic Random Access Memory is the lowest cost, highest density random access memory available. Nowadays, computers use DRAM for main memory. However, it’s access time is more compared to SRAM. The memory size of DRAM lies between 16 to 256 MB.

3. The DRAM stores its binary information on __________
A. MOSFET
B. Transistor
C. Capacitor
D. BJT
Answer: C
Clarification: Capacitor has high storing capability only, so DRAM stores its binary information in the form of electric charges on capacitors. However, DRAM takes more time time to access data.

4. Most modern operating systems employ a method of extending RAM capacity, known as __________
A. Magnetic memory
B. Virtual memory
C. Storage memory
D. Static memory
Answer: B
Clarification: Most modern operating systems employ a method of extending RAM capacity, known as virtual memory. Virtual memory is seen as part of main memory but is actually a secondary memory.

5. DRAM uses of integrated MOS capacitors as _______ instead of a flip-flop.
A. Storage cell
B. Memory cell
C. Dynamic cell
D. Static cell
Answer: B
Clarification: DRAM uses of integrated MOS capacitors as memory cell instead of a flip-flop. The advantage of this cell is that it allows very large memory arrays to be constructed on a chip at a lower cost per bit than in static memories.

6. What is the disadvantage of MOS capacitor in DRAM?
A. It can’t hold the data till a long period
B. It doesn’t holds the charge till a long period
C. It is highly densed
D. It is not flexible
Answer: B
Clarification: The disadvantage of MOS capacitor in DRAM is that it can’t hold the stored charge over a long period of time and it has to be refreshed every few millisecond. Thus, DRAM is slow in operation.

7. The dynamic RAM offers __________
A. High power consumption, large storage capacity
B. Reduced power consumption, large storage capacity
C. Reduced power consumption, short storage capacity
D. High power consumption, short storage capacity
Answer: B
Clarification: The dynamic RAM offers reduced power consumption and large storage capacity in a single memory chip. With the availability of such high packing density memory ICs, the capacity of memory will continue to grow. However, it’s access time is more and thus operation is slow.

8. The main memory of a PC is made of __________
A. Cache
B. Dynamic RAM
C. Static RAM
D. Both cache and dynamic RAM
Answer: D
Clarification: The main memory of a PC is made of cache and DRAM. DRAM offers reduced power consumption and large storage capacity in a single memory chip.

9. Virtual memory consists of __________
A. SRAM
B. DRAM
C. Magnetic memory
D. Main Memory
Answer: A
Clarification: Most modern operating systems employ a method of extending RAM capacity, known as virtual memory which consists of SRAM.

10. Dynamic RAM is used as main memory in a computer system as __________
A. It has a lower cell density
B. It needs refreshing circuitry
C. Consumes less power
D. Has higher speed
Answer: D
Clarification: Dynamic RAM is used as main memory in a computer system as it has a higher speed due to the presence of MOSFET technology. However, it’s access time is more compared to SRAM and operation is slow.

11. Cache memory acts between __________
A. RAM and ROM
B. CPU and RAM
C. CPU and Hard Disk
D. CPU and ROM
Answer: B
Clarification: In a computer, cache memory acts between CPU and RAM.

12. Which characteristic of RAM memory makes it not suitable for permanent storage?
A. Unreliable
B. Too slow
C. Too bulky
D. It is volatile
Answer: D
Clarification: RAM is volatile. Therefore, it stores data only as long as the d.c power is on.

13. Why do a DRAM employ the address multiplexing technique?
A. To reduce the number of memory locations
B. To increase the number of memory locations
C. To reduce the number of address lines
D. To increase the number of address lines
Answer: C
Clarification: A Dynamic RAM usually employs a technique called address multiplexing to reduce the number of address lines and thus the number of input/output pins on the IC package.

14. An address multiplexing in DRAM is of _____ bits.
A. 10240
B. 15289
C. 16384
D. 17654
Answer: C
Clarification: A Dynamic RAM usually employs a technique called address multiplexing to reduce the number of address lines and thus the number of input/output pins on the IC package. Address multiplexing has 2¹⁴ = 16384 bits.

15. What is a sense amplifier?
A. It is an amplifier which converts ac current into dc current
B. It is an amplifier which lowers the input voltage
C. It is an amplifier which increases the input voltage
D. It is an amplifier which converts the low voltage to a sufficient voltage
Answer: D
Clarification: A sense amplifier for each column is necessary to convert from the low voltage and low energy to a sufficient level on the I/O data line.

tough questions and answers on all areas of Digital Electronic Circuits,

Digital Electronics/Circuits Multiple Choice Questions on “Number System – 1”.

1. Any signed negative binary number is recognised by its ________
A. MSB
B. LSB
C. Byte
D. Nibble
Answer: A
Clarification: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

2. The parameter through which 16 distinct values can be represented is known as ________
A. Bit
B. Byte
C. Word
D. Nibble
Answer: C
Clarification: It can be represented up to 16 different values with the help of a Word. Nibble is a combination of four bits and Byte is a combination of 8 bits. It is “word” that is said to be a collection of 16-bits on most of the systems.

3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
A. Dividing
B. Multiplying
C. Adding
D. Subtracting
Answer: B
Clarification: On multiplying the decimal number continuously by 2, the binary equivalent is obtained by the collection of the integer part. However, if it’s an integer, then it’s binary equivalent is determined by dividing the number by 2 and collecting the remainders.

4. The representation of octal number (532.2)8 in decimal is ________
A. (346.25)10
B. (532.864)10
C. (340.67)10
D. (531.668)10
Answer: A
Clarification: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(532.2)8 = 5 * 8² + 3 * 8¹ + 2 * 8⁰ + 2 * 8^-1 = (346.25)10

5. The decimal equivalent of the binary number (1011.011)2 is ________
A. (11.375)10
B. (10.123)10
C. (11.175)10
D. (9.23)10
Answer: A
Clarification: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
1 * 2³ + 0 * 2² + 1 * 2¹ +1*2⁰ + 0 * 2^-1 +1 * 2^-2 + 1 * 2^-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10

6. An important drawback of binary system is ________
A. It requires very large string of 1’s and 0’s to represent a decimal number
B. It requires sparingly small string of 1’s and 0’s to represent a decimal number
C. It requires large string of 1’s and small string of 0’s to represent a decimal number
D. It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: A
Clarification: The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for calculation purposes as it compresses the long binary strings into small parts.

7. The decimal equivalent of the octal number (645)₈ is ______
A. (450)₁₀
B. (451)₁₀
C. (421)₁₀
D. (501)₁₀
Answer: C
Clarification: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
The decimal equivalent of the octal number (645)₈ is 6 * 8² + 4 * 8¹ + 5 * 8⁰ = 6 * 64 + 4 * 8 + 5 = 384 + 32 + 5 = (421)₁₀.

8. The largest two digit hexadecimal number is ________
A. (FE)16
B. (FD.16
C. (FF)16
D. (EF)16
Answer: C
Clarification: (FE)16 is 254 in decimal system, while (FD.16 is 253. (EF)16 is 239 in decimal system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.

9. Representation of hexadecimal number (6DE)H in decimal:
A. 6 * 16² + 13 * 16¹ + 14 * 16⁰
B. 6 * 16² + 12 * 16¹ + 13 * 16⁰
C. 6 * 16² + 11 * 16¹ + 14 * 16⁰
D. 6 * 16² + 14 * 16¹ + 15 * 16⁰
Answer: A
Clarification: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 16² + 13 * 16¹ + 14 * 16⁰.

10. The quantity of double word is ________
A. 16 bits
B. 32 bits
C. 4 bits
D. 8 bits
Answer: B
Clarification: One word means 16 bits, Thus, the quantity of double word is 32 bits.

his set of Digital Electronics/Circuits Multiple Choice Questions on “Diode-Transistor Logic(DTL)”.

1. Diode–transistor logic (DTL) is the direct ancestor of _____________
A. Register-transistor logic
B. Transistor–transistor logic
C. High threshold logic
D. Emitter Coupled Logic
Answer: B
Clarification: Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic. To overcome the shortcomings of DTL, TTL came into existence.

2. In DTL logic gating function is performed by ___________
A. Diode
B. Transistor
C. Inductor
D. Capacitor
Answer: A
Clarification: Diode serves as the input network and the switching operation is performed by the transistor.

3. In DTL amplifying function is performed by ___________
A. Diode
B. Transistor
C. Inductor
D. Capacitor
Answer: B
Clarification: The amplifying and switching function is performed by a transistor and the diode acts an input network in DTL.

4. How many stages a DTL consist of?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: The DTL circuit shown in the picture consists of three stages: an input diode logic stage, an intermediate level shifting stage and an output common-emitter amplifier stage.

5. The full form of CTDL is ___________
A. Complemented transistor diode logic
B. Complemented transistor direct logic
C. Complementary transistor diode logic
D. Complementary transistor direct logic
Answer: A
Clarification: The full form of CTDL is Complemented transistor diode logic.

6. The DTL propagation delay is relatively ___________
A. Large
B. Small
C. Moderate
D. Negligible
Answer: A
Clarification: Propagation delay refers to the time taken by the output to change it’s state when the input is altered. When the transistor goes into saturation from all inputs being high charge is stored in the base region. When it comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time which results as a large propagation delay. Thus, it has small clock frequency.

7. The way to speed up DTL is to add an across intermediate resister is ___________
A. Small “speed-up” capacitor
B. Large “speed-up” capacitor
C. Small “speed-up” transistor
D. Large ” speed-up” transistor
Answer: A
Clarification: One way to speed up DTL is to add a small “speed-up” capacitor across intermediate resister. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the transistor by increasing the initial base drive.

8. The process to avoid saturating the switching transistor is performed by ___________
A. Baker clamp
B. James R. Biard
C. Chris Brown
D. Totem-Pole
Answer: A
Clarification: Another way to speed up DTL other than adding a small “speed-up” capacitor across intermediate resister is to avoid saturating the switching transistor which can be done with a Baker clamp. The name Baker clamp is given at the name of Richard H. Baker, who described it in his 1956 technical report “Maximum Efficiency Switching Circuits”.

9. A major advantage of DTL over the earlier resistor–transistor logic is the ___________
A. Increased fan out
B. Increased fan in
C. Decreased fan out
D. Decreased fan in
Answer: B
Clarification: A major advantage over the earlier resistor–transistor logic is the increased fan in. Fan-in is the measure of the maximum number of inputs that a single gate output can accept.

10. To increase fan-out of the gate in DTL ___________
A. An additional capacitor may be used
B. An additional resister may be used
C. An additional transistor and diode may be used
D. Only an additional diode may be used
Answer: C
Clarification: To increase fan-out of the gate in DTL, an additional transistor and diode may be used. Here, the fan out means the number of maximum input that a single gate output can feed.

11. A disadvantage of DTL is ___________
A. The input transistor to the resister
B. The input resister to the transistor
C. The increased fan-in
D. The increased fan-out
Answer: B
Clarification: A disadvantage of DTL is the input resistor to the transistor and its presence tends to slow the circuit down. Hence limiting the speed at which the transistor is able to switch states. Thus, the propagation delay increases.

Digital Electronics/Circuits Multiple Choice Questions on “Fast Adder & Serial Adder – 1”.

1. The inverter can be produced with how many NAND gates?
A. 2
B. 1
C. 3
D. 4
Answer: B
Clarification: The inverter can be produced with the help of single NAND gate, because we can send a single input twice through the same NAND gate together, thus producing the inverted version of the input as output. It works as an inverter.

2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output’s relation with the inputs?
A. The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses
B. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses
C. The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
D. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
Answer: D
Clarification: When both the input pulses are high or low X-OR output is low. But when one of the input is high and another is low or vice-versa, output is high. In this problem for the first 20uS one input is high and another is low. So, obviously output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15) first input is still high and second one is low so output is high.

3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: Since in the given expression two inputs are complemented. So, we require two NOT gate at the input. A NOT gate is a basic gate which accepts a single input and produces a single output, which is the inverted version of the input.

4. The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and ________ if a high order carry is generated.
A. Addend, minuend
B. Minuend, subtrahend
C. Addend, minuend
D. Augend, addend
Answer: D
Clarification: The carry look ahead adder is based on the principle of looking at the lower order bits of the augend and addend if a high order carry is generated. A carry look ahead adder is a type of adder which reduces the propagation delay.

5. What are carry generate combinations?
A. If all the input are same then a carry is generated
B. If all of the output are independent of the inputs
C. If all of the input are dependent on the output
D. If all of the output are dependent on the input
Answer: B
Clarification: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate combinations.

6. In serial addition, the addition is carried out __________
A. 3 bit per second
B. Byte by byte
C. Bit by bit
D. All bits at the same time
Answer: C
Clarification: In serial addition, the addition is carried out bit by bit.

7. How many shift registers are used in a 4 bit serial adder?
A. 4
B. 3
C. 2
D. 5
Answer: C
Clarification: There are two shift registers are used in a 4-bit serial adder, which is used to store the numbers to be added serially. Serial addition takes place bit by bit.

8. A D flip-flop is used in a 4-bit serial adder, why?
A. It is used to invert the input of the full adder
B. It is used to store the output of the full adder
C. It is used to store the carry output of the full adder
D. It is used to store the sum output of the full adder
Answer: C
Clarification: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be added to the next significant position of the numbers in the registers.

9. What is ripple carry adder?
A. The carry output of the lower order stage is connected to the carry input of the next higher order stage
B. The carry input of the lower order stage is connected to the carry output of the next higher order stage
C. The carry output of the higher order stage is connected to the carry input of the next lower order stage
D. The carry input of the higher order stage is connected to the carry output of the lower order stage
Answer: A
Clarification: When the carry output of the lower order stage is connected to the carry input of the next higher order stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.

10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be __________
A. 0
B. 1
C. Floating
D. High Impedance
Answer: B
Clarification: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step (i.e 0 – 1 – 1 = 0, borrow = 1).