Category: VHDL Objective Questions

This set of Advanced VHDL Questions and Answers on “Entity and Its Declaration”.

1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals
Answer: d
Clarification: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions.

2. Which of the following can be the name of an entity?
a) NAND
b) Nand_gate
c) Nand gate
d) AND
Answer: b
Clarification: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option b is the only legal word.

3. Which of the following is correct syntax for entity declaration?
a)

ENTITY entity_name IS
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END entity_name;

b)

 ENTITY entity_name
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

c)

ENTITY entity_name IS
    PORT port_name
    ( signal_names : signal_modes signal_type;
    signal_names : signal_modes signal_type);
   END entity_name;

d)

ENTITY entity_name
    PORT port_name
    (signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

View Answer

Answer: a
Clarification: The correct syntax for declaring an entity block starts with reserve word ENTITY followed by name of entity and the next is reserve word IS. Name of entity can contain letters, numbers and underscore character. After this, PORT declaration is used. PORT declaration is used to declare the interface signals for the entity and to assign mode and type of data. The declaration is completed by using END operator and the entity name.

4. Refer to the VHDL code given below, how many input-output pins are there in MUX entity?

ENTITY mux IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END mux;

a) 5
b) 4
c) 3
d) 2
Answer: c
Clarification: In the given declaration, entity has 3 I/O pins. The signals a and b are Input signals and y is the output signal. So, we can say that the declaration is for 2:1 MUX. In this way, we can find the number of I/O pins from the entity declaration.

5. The entity name ‘xyz’ and ‘XYZ’ will be treated the same.
a) True
b) False
Answer: a
Clarification: VHDL is a strongly typed language which means that there are very strict rules regarding the data types. But, there is no difference between names of entity. VHDL is not case sensitive therefore, ‘xyz’ and ‘XYZ’ are same.

6. Which of the following mode of the signal is bidirectional?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Clarification: INOUT is the only bidirectional mode for any signal. IN, OUT and BUFFER are unidirectional mode since they specifies the type to be either input or output. INOUT can be used as both an input to an entity and as an output of the entity. We can read as well as assign the value for INOUT type signal.

7. In an assignment statement, OUT signal can be used only to the ___________
a) Left of <= operator
b) Right of <= operator
c) Any side of <= operator
d) Right of := operator
Answer: a
Clarification: OUT signal is used to take an output from any entity. Therefore, we can assign it any value but can’t read any value from this type of signal. So, in an assignment statement, OUT type signal can be used on the left side of <= operator.

8. On which side of assignment operator, we can use the IN type signal?
a) Left
b) Right
c) Both
d) Can’t be used
Answer: b
Clarification: IN signal is for input only. We can read the value from IN signal. Therefore, it can be placed only on the right side of assignment.

9. What is the difference between OUT and BUFFER?
a) BUFFER can’t be used inside the entity for reading the value and OUT can be
b) BUFFER can only be read whereas OUT can only be assigned a value
c) BUFFER can be read as well as assigned a value but OUT can only be assigned
d) Both are same
Answer: c
Clarification: BUFFER is a unidirectional mode used as an output from the entity. But, the value of BUFFER can be used inside the entity i.e. it can appear on both sides of assignment operator whereas the value of OUT can’t be used inside the entity and can appear on the left side of assignment operator.

10. GENERICs are not declared in the entity.
a) True
b) False
Answer: b
Clarification: The declaration of GENERICs is also done in the entity itself. It is used to declare the constants that can be used to control the structure of behavior of the entity. The Generics are declared before port declarations.

11. Which of the following is an entity declared for a full adder?
a)

ENTITY full_adder IS
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

b)

ENTITY full_adder IS
    PORT (a ,b : IN BIT;
    s, c : OUT BIT);
    END full_adder;

c)

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

d)

ENTITY full_adder IS
    PORT (a, b, c, s, co : BIT);
    END full_adder;

View Answer

Answer: a
Clarification: A full adder has three inputs and two outputs. Inputs are two bits to be added and some carry. Outputs are sum and carry. Therefore, option a shows the correct declaration of entity full_adder. In this, a and b are the bits to be added and c is the input carry whereas, s is the sum output and co is the carry output.

12. How to control the structure and timing of the entity can be changed?
a) By using TIME variable in the entity
b) By changing the entity declaration from time to time
c) By using some special code
d) By using GENERICS
Answer: d
Clarification: The structure and timing constraints can be changed by declaring some constant using GENERICS declaration. For example, in the full adder example, number of bits to be added can be declared as array with its size N. this N can be declared as a constant in the GENERIC declaration part of entity. By changing N only, one can change number of bits for the addition.

13. Which of the following can have more than one driver?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Clarification: INOUT is the only bidirectional signal. This mode can have more than one driver. Therefore, INOUT can be driven by more than one drivers. All other modes like IN, OUT, BUFFER can have only one driver.

14. Which of the following is the default mode for a port variable?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: a
Clarification: IN is the default mode for a port variable. If the mode of any signal is not specified in the port declaration, then it is considered as IN type signal. All other types are needed to be specified at the time of declaration.

advanced questions and answers on all areas of VHDL, .

This set of VHDL test on “Signal Assignment – 2”.

1. The selected concurrent statement is equivalent to ________ sequential statement.
a) If else
b) Loop
c) Wait
d) Case
Answer: d
Clarification: Selected concurrent assignment statement is used when the target signal has to choose one value out of n(say) values. This is similar to the case statement used in the process. It uses the keyword ‘SELECT’ to select one value.

2. Those statement which are placed under ________ are concurrent.
a) Process
b) Function
c) Architecture
d) Procedure
Answer: c
Clarification: VHDL code, in general, is a concurrent code. Only statements placed under Process, Function or Procedure are executed sequentially. All other statements are concurrent statements.

3. In case of concurrent assignment, order of statements doesn’t matter.
a) True
b) False
Answer: a
Clarification: Since execution of a concurrent statement is parallel and an assignment statement has to be executed whenever the signal associated with it changes its value. Therefore, there is no restriction on the order of the statements.

4. Which of the following can’t be implemented with concurrent statements only?
a) Multiplexer
b) Decoder
c) Adder
d) Counter
Answer: d
Clarification: In general, we use concurrent code to build combinational circuits and the reason is that order of statements is not a problem. So, we can’t use purely concurrent code to obtain sequential logic circuits due to use of clock and processes. Hence, counter can’t be designed by using concurrent code only.

5. Variable assignment statement executes in ______ time.
a) Immediately(zero)
b) After delay specified
c) After one clock cycle
d) After two clock cycles
Answer: a
Clarification: When a variable is assigned a value, the assignment executes in zero simulation time. In other words, it changes the value of variable immediately. Also, the delay mechanism is used in the signal assignment but not in variable assignment. Variable assignment doesn’t use any delay mechanism.

6. In the signal assignment statement, which delay is used?

a) Transport delay
b) Inertial delay
c) Delta delay
d) Wire delay
Answer: b
Clarification: Inertial delay is the default delay in VHDL in which only last value is persisted ignoring all other delays. In the case of inertial delay, there is no need of specifying anything like we need to write TRANSPORT to specify the transport delay.

7. Inertial delay in Signal assignment is useful to ___________
a) Specify wire delay
b) Accumulate delay
c) Ignore input glitches
d) No use
Answer: c
Clarification: Inertial delay assignment takes only last assignment statement into consideration ignoring all the preceding assignments. So, any intermediate change will be ignored. Therefore, It is useful in ignoring input glitches.

8. Which of the following statement is a zero delay statement?
a) y <= x AFTER 10 ns
b) y <= TRANSPORT x AFTER 10 ns
c) y <= x
d) y := x AFTER 10 ns
Answer: d
Clarification: Signal assignment always have some amount of delay either inertial or transport. If there is no delay specified in signal assignment, even then the delta delay is used to assign value. Only variable assignment is executed immediately also the delay is ignored. Therefore, option d is zero delay statement.

9. Which of the following statement can’t be used to assign values in behavioral modeling of OR Gate?
a) Simple concurrent assignment
b) Sequential assignment
c) Conditional concurrent assignment
d) Selected concurrent assignment
Answer: d
Clarification: In the behavioral modeling, various output values are described w.r.t different combination of input values. A conditional concurrent assignment and selected concurrent assignment can add some condition for assigning values. Same can be done with sequential statements. By using simple concurrent statements, it is not possible to realize or gate.

10. Which of the following is not an assignment statement?
a) <=
b) :=
c) =>
d) :>
Answer: d
Clarification: There are three assignment statements in VHDL. <= is a signal assignment statement, := is used for variable assignment and => is used at the time of mapping the components and is used with ‘OTHERS’. These are 3 type of assignment operators.

11. OTHERS keyword is used with which kind of assignment?
a) Concurrent
b) Sequential
c) Selected
d) Conditional
Answer: c
Clarification: Selected concurrent assignment statement is used when you have to choose one value out of n values. In that case WHEN and OTHERS keywords are used. OTHERS is similar to the ELSE statement which will be selected when all the conditions are false.

12. The following code represents which of the logic gates?

WITH ab SELECT 
y <= 1 WHEN “11”;0	WHEN OTHERS;

a) And gate
b) Or gate
c) Not gate
d) Nand gate
Answer: a
Clarification: Here, the selected signal assignment is used in which the output is getting the value 1 when both the inputs are 1. Otherwise, the output is 0. This is clearly the case of 2 inputs AND gate.

VHDL for tests, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Functions and Subprograms – 1”.

1. Functions and subprograms are both same.
a) True
b) False
Answer: b
Clarification: A subprogram consists of procedures and functions. Both of them are collectively called subprograms. So, subprogram is not same as a function but a function is a part of subprogram in case of VHDL.

2. A function is a ________ code.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process oriented
Answer: b
Clarification: A function is a section of sequential code. From the construction point of view, functions are very similar to the process. They employ all the sequential statements like IF, CASE etc.

3. Which of the following sequential statement can’t be used in a function?
a) WAIT
b) IF
c) CASE
d) LOOP
Answer: a
Clarification: A function can contain any kind of sequential statement may it be IF statement, CASE statement, LOOP statement, NEXT, EXIT or NULL. The only exception is the WAIT statement. One can’t use a WAIT statement inside a function.

4. What is the correct syntax for declaration of a function?
a)

     FUNCTION function_name (parameter_list) RETURN return_type IS
     declaration_part;
     BEGIN
     sequential_statements;
     END FUNCTION;

b)

     FUNCTION function_name (parameter_list) RETURN return_type IS
     BEGIN 
     declaration_part;
     sequential_statements;
     RETURN expression;
     END FUNCTION;

c)

    FUNCTION function_name (parameter_list) RETURN return_type IS
     BEGIN
     declaration_part;
     sequential_statements;
     RETURN expression;
     END function_name;

d)

     FUNCTION function_name (parameter_list) RETURN return_type IS
     declaration_part;
     BEGIN
     sequential_statements;
     RETURN expression;
     END function_name;

View Answer

Answer: d
Clarification: The function is defined in the way shown in option d. The keyword FUNCTION is followed by the name of function which in turn is followed by the list of parameters in a parenthesis. After the list of parameters the return type of a function is specified followed by the declaration part of the function in which local variables can be declared. The declaration part and statement part is separated by keyword BEGIN. Then there is the RETURN statement and the function definition is end by END and function name.

5. The function is called from the ________
a) Function itself
b) Library
c) Main code
d) Package
Answer: c
Clarification: The function which is once declared is always called from the main code. Whenever a function call occurs, the control is passed to the space where the function is defined. Then, the function is executed till a RETURN statement comes, which returns the control to main code.

6. The parameters used at the time of function call are called _________
a) Formal parameters
b) Actual parameters
c) Real parameters
d) Complex parameters
Answer: b
Clarification: The parameters which are specified at the time of function call are called the Actual parameters whereas the parameters used at the time of function definition are called formal parameters. The values from actual parameters are copied to the formal parameters in the same order as specified.

7. Functions are always invoked as a(n) _________
a) Constant
b) Variable
c) Signal
d) Expression
Answer: d
Clarification: Any function having a return type is always invoked as an expression. The expression is solved in the function definition and the result is specified by the return statement which can be taken as the result of the expression itself.

8. How many return arguments can be there in the function?
a) 1
b) 2
c) 3
d) 4
Answer: a
Clarification: It is very important thing to note that one function can return at most one value. The expression which is used in the return statement must result in the same type as that of return type specified in the definition. The value from the return expression is then returned to the main code.

9. Which of the following can’t be the parameter of function?

SIGNAL a, b : IN STD_LOGIC
VARIABLE c : INTEGER
CONSTANT d : INTEGER

a) a
b) b
c) c
d) d
Answer: c
Clarification: The parameter of a function can either be a signal or a constant. The variable can’t be used as a parameter of a function. Any of the data types which are synthesizable are allowed to use as a type of signals or constants.

10. A function call can be a concurrent as well as a sequential statement.
a) True
b) False
Answer: a
Clarification: The function can be called in the concurrent part of the code and it can be called in the sequential part of the code. It is not necessary that a function can be called inside a process only. However, it may be noted that the function itself contains only sequential statements.

This set of VHDL Problems on “All Keywords in VHDL – 3”.

1. The use of NEXT in VHDL is similar to _________ in C.
a) Break
b) Continue
c) Exit
d) Do
Answer: b
Clarification: NEXT statement is used to skip the current iteration of the loop and start with the next iteration. The same is being done by the continue statement is traditional programming languages like C, C++, etc.

2. NULL keyword is most of the time useful with _______ part of _______ statement.
a) IF, IF
b) ELSIF, IF
c) OTHERS, CASE
d) NEXT, LOOP
Answer: c
Clarification: NULL keyword is useful in situations where we have to explicitly specify that no action is needed. It is generally useful in the CASE statement with OTHERS. When all the cases are specified and we don’t want to perform anything when any other case occurs, then it can be used.

3. When a port of a component is not connected to any signal, then which of the following keyword is used to indicate the situation?
a) OPEN
b) CLOSED
c) ON
d) OFF
Answer: a
Clarification: When any of the port is not connected to any signal in the component instantiation statement, then OPEN keyword is used in the association list of the statement to indicate the open port.

4. Which of the line(s) in following code is not legal?

L1 : PROCESS(a,b)
L2 : SIGNAL x;
L3 : BEGIN
L4 : c<= a AFTER 10 ns;
L5: END PROCESS

a) L2 only
b) L4 only
c) No error
d) Both L2 and L4
Answer: d
Clarification: A SIGNAL keyword is used to declare a signal which can’t be declared inside a process. So, L2 isn’t legal. Similarly, there is no role of delay for a sequential assignment statement. So, AFTER keyword is valid for concurrent assignment statement only.

5. A POSTPONED keyword used with a process will make it wait till _________
a) A specific process is suspended
b) A signal from the sensitivity list changes
c) All the processes are suspended
d) All the signals in sensitivity list changes
Answer: c
Clarification: A POSTPONED process is the one which is executed after the end of all processes. When all of the normal processes are suspended then the execution of postponed process starts.

6. Which of the following keyword is used to identify a clocked process?
a) CLOCKED
b) CLKED
c) SEQ
d) No specific keyword
Answer: d
Clarification: A clocked process also looks like a simple process. The only difference being a clock signal is used inside a clocked process. Whenever the clock event is identified or clock is simply used in the process then it is called a clocked process.

7. RANGE keyword is always used in _______
a) Type declaration
b) Array declaration
c) Loop declaration
d) Process declaration
Answer: a
Clarification: A Type declaration always includes three parts. The name of the Type, the base type and the range for the type. This range is always declared by using keyword RANGE followed by some values.

8. If we don’t use any keyword in the function definition, then which of the following is the type of function?
a) IMPURE
b) PURE
c) CASE
d) CONCURRENT
Answer: b
Clarification: There are two kinds of functions which are PURE and IMPURE. A function by default is considered as a pure function. If we want to declare an impure function then we need to write IMPURE, but this is not in the case of Pure function.

9. The REPORT keyword is usually associated with _______
a) RECORD
b) NULL
c) ASSERT
d) IF
Answer: c
Clarification: REPORT keyword is used with ASSERT statement. Assert statement checks the consistency of simulation and execution and report in conjunction with assert is used to report the kind of error through a message.

10. On which side of a signal assignment statement, UNAFFECTED keyword can be used?
a) Left hand side
b) Right hand side
c) On any of the side
d) Can’t be used in an assignment statement
Answer: b
Clarification: UNAFFECTED is a keyword used when we need not to assign a new value to the signal. This is the case used in a selected or conditional signal assignment statements. So, it can be used as a part of waveform only i.e. on the right hand side only.

VHDL Problems, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “RTL Simulation”.

1. What does RTL in digital circuit design stand for?
a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic
Answer: c
Clarification: RTL in digital circuit design stands for register transfer level, used in HDL. Register transfer language is a type of intermediate representation close to assembly language. Resistor-transistor logic is used in BJTs as switching devices. Register transfer logic is used in state machine designs.

2. RTL is a design abstraction of what kind of circuit?
a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit
Answer: b
Clarification: RTL is a design abstraction that shapes a synchronous digital circuit with reference to digital signals that flow between hardware registers and the logical operations are carried out on those signals.

3. RTL is used in HDL to create what level of representations in the circuit?
a) High-level
b) Low-level
c) Mid-level
d) Same level
Answer: a
Clarification: RTL is used in HDL for creating HIGH-LEVEL of representations in the circuit, from which lower-level of representations can be derived. Designing at the RTL level is a representative practice in modern digital design.

4. RTL mainly on describing the flow of signals between ________
a) Logic gates
b) Registers
c) Clock
d) Inverter
Answer: b
Clarification: RTL on describing the flow of signals between registers. There is a regularly repeated path of logic from the output of the register to its input, that is the reason it is called register transfer level.

5. Which flip-flop is usually used in the implementation of the registers?
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) J-K flip-flop
Answer: a
Clarification: Registers are generally implemented as D flip-flops because connection for the shift register is the simplest with D flip-flop, as there is a single data input in it. The flip-flop also stores the output of whatever logic is applied to its data input as long as the clock input is high.

6. Which of the following tool performs logic optimization?
a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler
Answer: b
Clarification: Synthesis tool performs logic optimization in RTL by converting high-level description of the design circuit into an optimized gate level representation by the use of basic logic gates like and, or, nor, etc.

7. RTL is a combination of both combinational and sequential circuits.
a) True
b) False
Answer: a
Clarification: RTL is a combination of both combinational and sequential circuits. Combinational logic performs all the logical operations in the circuit and it typically consists of basic logic gates and registers make synchronized sequential logic.

8. Setup time is the time required for input data to settle after the triggering edge of the clock.
a) True
b) False
Answer: b
Clarification: The time required for an input data to settle BEFORE the triggering edge of the clock is called the setup time. It is measured with respect to active clock pulse edge only.

9. Hold time is the time needed for the data to ________ after the edge of the clock is triggered.
a) Decrease
b) Increase
c) Remain constant
d) Negate
Answer: c
Clarification: Hold time is the time needed for the data to remain constant after the edge of the clock is triggered. Data must remain stable, if the incorrect data is latched then, it leads to hold violation.

10. Simulator enters in which phase after the initialization phase?
a) Execution phase
b) Compilation phase
c) Elaboration phase
d) Simulation phase
Answer: a
Clarification: Simulator enters in execution phase after the initialization phase, the actual simulation of the behaviour of the design takes place in the execution phase. Each simulation process in the active queue is taken out and executed until it suspends.

11. Conversion of RTL description to Boolean _______ description is a function of the translation procedure in the synthesis process.
a) Optimized
b) Unoptimized
c) Translation
d) PLA format
Answer: b
Clarification: Conversion of RTL description to Boolean unoptimized description is a function of translation procedure in the synthesis process. The logic synthesis tool converts the description to an unoptimized, intermediate, internal representation.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Architecture”.

1. What does the architecture of an entity define?
a) External interface
b) Internal functionality
c) Ports of the entity
d) Specifications
Answer: b
Clarification: Basically, entity describes the interface to the VHDL model and its architecture describes the internal view of that entity. It describes the functionality and contains the statements which describe the behavior of entity.

2. Which of the following is the correct syntax for architecture declaration and definition?
a)

ARCHITECTURE architecture_type OF entity_name IS
     Declarations_for_architecture;
     BEGIN
     Code;
     ….
    END architecture_name;

b)

ARCHITECTURE architecture_name OF entity_name IS
     BEGIN
     Declarations_for_architecture;
     Code;
     ….
    END architecture_name;

c)

ARCHITECTURE architecture_type OF entity_name IS
     BEGIN
     Declarations_for_architecture;
     Code;
     ….
    END architecture_type;

d)

ARCHITECTURE architecture_name OF entity_name IS
     Declarations_for_architecture
     BEGIN
     Code;
     ….
     END architecture_name;

View Answer

Answer: d
Clarification: Architecture has two parts which are declarative part and the code part containing concurrent and sequential statements. Declaration part is optional but the code part is essential. The declaration of architecture is started with the keyword ARCHITECTURE followed by its name and then the name of entity. Then, the declaration part is used to declare and then BEGIN keyword is used to start the code part.

3. What does the declarative part of architecture contain?
a) Declaration of another entity
b) Declaration of libraries and packages
c) Declaration of local signals, constants or subprograms
d) Declaration of Architecture type
Answer: c
Clarification: Declarative part is the optional part of architecture definition. In this section, the local signals, constants, variables or subprograms are declared which are needed in the architecture. The scope of variables declared in this region is limited to the architecture only.

4. The statements in between the keyword BEGIN and END are called _______
a) Concurrent statements
b) Netlist
c) Declaration statement
d) Entity function
Answer: a
Clarification: The proper word for the statements between BEGIN and END is Concurrent statements since they are executed concurrently. The code in between BEGIN and END describes the functionality or structure of the entity. BEGIN keyword specifies the starting of code.

5. Which of the following is the correct architecture for a simple Nand gate?
a)

ARCHITECTURE my_arch OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END my_arch;

b)

BEGIN
     ARCHITECTURE my_arch OF nand_gate IS
    x <= a NAND b;
    END behavioral;

c)

BEGIN
    ARCHITECTURE behavioral OF nand_gate IS
    x <= a NAND b;
    END my_arch;

d)

ARCHITECTURE nand OF nand_gate IS
    BEGIN
    x <= a NAND b;
    END nand;

View Answer

Answer: a
Clarification: For correct syntax, the word ARCHITECTURE must be followed by the name of architecture which may not contain the reserved words. After which BEGIN keyword is used to show the beginning of code section of the architecture and at last END keyword is used followed by name of architecture. Therefore, only option a is correct architecture of NAND gate explaining its functionality.

6. Which of the following can be the name of an architecture?
a) arch 1
b) 1arch
c) arch_1
d) architecture
Answer: c
Clarification: The name of architecture is its identifier and hence, it will follow the same rule as that of identifiers. It may contain alphanumeric characters and underscore character starting with alphabet always. Also, name can’t be same as any of the reserved word of VHDL.

7. An entity can’t be described by more than one architecture.
a) True
b) False
Answer: b
Clarification: It is false that an entity can’t have two or more architectures. An entity can be described by using more than one architecture. For an instance, one can define its behavior and another can explain its structure. However, the converse of the statement is not true, one architecture can describe only one entity.

8. Which of the following can’t be declared in the declaration part of the architecture?
a) Signals
b) Subprograms
c) Components
d) Libraries
Answer: d
Clarification: In the declaration part of architecture, the local data objects and subprograms are defined which can be used in the architecture only. However, a library contains packages which are generally used in every VHDL model and they are declared globally at the starting of VHDL code.

9. It is not possible to declare an entity after declaring its architecture.
a) True
b) False
Answer: a
Clarification: An entity is required first to describe its architecture. First of all, entity create an external interface of the system after which we can describe the internal view of entity. Until there is no entity, architecture declaration is not possible.

10. Which of the following statements execute faster?
a) Sequential statements
b) Concurrent statements
c) Declaration statements
d) Loop statements
Answer: b
Clarification: Concurrent statements execute faster than sequential statements. Sequential statements are those which are executed one after another whereas concurrent statements execute concurrently or simultaneously. Therefore, concurrent are faster.