Category: VHDL Objective Questions

This set of VHDL Interview Questions and Answers for Experienced people on “Structural Modeling – 3”.

1. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation
Answer: a
Clarification: In a VHDL code, first of all, the packages and libraries are declared which are then followed by entity declaration. After the entity is declared, to model a circuit on the structural level, first all the components are declared after which they can be instantiated.

2. Refer to the model given below, which circuit is designed?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;

a) Half adder
b) Comparator 2- bits
c) Full adder
d) Can’t be determined
Answer: b
Clarification: Though it is not possible to determine the circuits through its structural model until its components are not specified. In the above case, the components are clearly 2 input AND, OR and EXOR gates. These gates are connected to give one output called x as the EXOR of three inputs a, b and c. Another output y = ab + bc+ ac. So, it is a full adder circuit designed.

3. There is a special function called interconnect () to define interconnections between pins.
a) True
b) False
Answer: b
Clarification: There is no special function for defining interconnection between two or more inputs or outputs. These interconnections are defined by using port map only. When we use same port for two or more components then they are interconnected.

4. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?

ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, y);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, x);
END arch1;

a) y
b) x
c) s5
d) c
Answer: a
Clarification: Since there are three components which are two inputs EXOR gate, AND gate and OR gate. The signal s1 is the output of EXOR of a and b inputs. This signal is further used to EXOR with c and the output is y. So, y = a EXOR b EXOR c, which corresponds to the sum output of the full adder.

5. Which modeling style is used in code given below?

ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
Architecture arch OF design IS
BEGIN
x <= a XOR b XOR c;
y <= (a AND b) OR (b AND c) OR (a AND c);
END arch;
ARCHITECTURE arch1 OF design IS
COMPONENT comp1 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp3 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: comp1 PORT MAP(a, b, s1);
X2 : comp1 PORT MAP(s1, c, x);
X3: comp2 PORT MAP(a, b, s2);
X4 : comp2 PORT MAP(a, c, s3);
X5: comp2 PORT MAP(b, c, s4);
X6: comp3 PORT MAP(s2, s3, s5);
X7: comp3 PORT MAP(s4, s5, y);
END arch1;

a) Behavioral and structural
b) Structural
c) Dataflow
d) Dataflow and Structural
Answer: d
Clarification: Since there are two architectures defined for the entity ‘design’. So, two modeling styles are used. In the first architecture, the data flow from inputs to outputs is described by using Boolean equations therefore, it is dataflow modeling. In the second architecture, components are declared and instantiated. So, it is structural model.

6. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)
b) label : component_name GENERIC MAP(parameter_list)
c) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
d) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
Answer: a
Clarification: Generic is a constant parameter which can be used in structural modeling. But, generic is not a component as such. It can be used as a specification to any component. The correct syntax to use a generic is GENERIC MAP followed by a PORT MAP function.

7. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False
Answer: b
Clarification: A Generic is just a constant and hence can’t have any input or output ports. It is only used with any component to describe its specification. For example, any component needs an array of input ports, the index value of that array can be defined by using generic parameter and that generic parameter can be used with PORT MAP to map the ports.

8. A component instantiation statement generates a(n) _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object
Answer: d
Clarification: By ending the component declaration, its object is created which can be used further in the code to use the declared component. The component instantiation statement uses this object and inherits the properties of component declared. These properties include all the ports and their number.

9. The structural code for 4-bit adder is given below.

COMPONENT adder IS
GENERIC (n : INTEGER := 3);
PORT(input : IN BIT_VECTOR(n DOWNTO 0);
output : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT;

If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component
Answer: a
Clarification: The only way to change it is by changing the value of n. If n is changed from 3 to 7, then it will have 8 input bits and 8 output bits. In this way, by using generic, the whole structure can be altered easily. Also, it may be noted if the value of the generic is not specified, then it will take the value used at the time of entity declaration.

10. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping
Answer: b
Clarification: Implicit mapping is another name for positional mapping in which only ports are specified without using any assignments. Similarly, nominal mapping is the other name for explicit mapping which uses proper assignments to instantiate the component. In VHDL, there are only two types of mapping called Positional and nominal, there is no mapping called inclusive mapping.

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This set of VHDL online quiz on “Signal vs Variables – 2”.

1. Which data object can’t be declared inside a process?
a) Signal
b) Variable
c) Constant
d) Integer
Answer: a
Clarification: A process consists of sequential statements and signals can be used inside the process. But, it is not possible to declare a signal inside the process. Variables, on the other hand, can be declared in a process.

2. When a signal is assigned a value inside a process, then the value of a signal is updated _________
a) Immediately
b) After one delta cycle
c) At the end of the corresponding process
d) At the end of architecture
Answer: c
Clarification: The signal is not updated immediately. The new value should not be expected to be ready before the conclusion of the corresponding process. It is updated at the end of the process and therefore, it is not recommended to assign two or more values to a signal in the same process since only last one is considered.

3. A variable is assigned a value inside a process, the new value of the variable will be available _______
a) After one delta cycle
b) Immediately
c) At the end of a process
d) At the end of architecture
Answer: b
Clarification: Unlike signals, the value of variable is updated immediately. In other words, we can say that the new value of the variable or its updated value can be used immediately in the next line of the code which is not the case with variables.

4. A variable can be used outside the process i.e. in the architecture.
a) True
b) False
Answer: b
Clarification: A variable can be used inside a process, function or procedure only. One can’t use it outside the process. The variables can’t be assigned values concurrently or in a parallel manner as we can do with the signals.

5. There are no delays in case of variables.
a) True
b) False
Answer: a
Clarification: As we know that the variables get their value at the same time or immediately. No delay can be used in the variable assignment. However, in signals there are two types of delay which are transport and inertial delays. This is not possible to use AFTER keyword in the variable assignment.

6. When there is no delay specified in a signal assignment (concurrent), the delay will be _______
a) Zero
b) Transport delay
c) Inertial delay
d) Delta delay
Answer: d
Clarification: In a concurrent assignment statement either transport or inertial delay is used. Even if there is zero delay specified it will consider delta delay before assigning a value to the signal. So, it is not possible to assign the value to signal immediately even if no delay is specified.

7. During synthesis, a variable infers ________
a) Flip flop
b) Register
c) Wire
d) Variables are not synthesizable
Answer: c
Clarification: Both signal and variable are synthesizable and variables infers a wire at the time of synthesis. However, the signal, unlike variable, infers a flip flop at the time of synthesis.

8. In which of the following, the right hand side of an assignment is a waveform element?
a) Signal
b) Variable
c) Constant
d) Process
Answer: a
Clarification: The right hand side of a signal assignment statement is a sequence of waveform elements. These elements are having associated time expressions or delays which are generally followed by AFTER keyword.

9. Which of the following needs no evaluation of drivers?
a) Signals
b) Variables
c) Process
d) Functions
Answer: b
Clarification: Signals have drivers associated with them which need evaluation and resolution (in case of multiple drivers). On the other hand, variable has no driver associated so no evaluation is required at the time of simulation. So, variables are cheaper to implement as compared to signals.

10. What is there in right hand side of a variable assignment?
a) Time expressions
b) Waveform elements
c) Delays
d) Simple expressions
Answer: d
Clarification: Unlike signals, there are no waveform elements and timing expressions on the right hand side of a variable assignment. The right hand side of a variable assignment is always an expression which can be any of the Boolean, arithmetic or logical.

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This set of VHDL Question Paper on “Generate Statement”.

1. Generate statement is a _______ statement.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process
Answer: a
Clarification: Generate statement is a concurrent statement that can be used in architecture directly. It is similar to loop statement in case of sequential statement. It give designer the ability to create replicated structures.

2. There are _______ types of GENERATE statement in VHDL.
a) 2
b) 3
c) 4
d) 5
Answer: a
Clarification: There are 2 types of GENERATE statement in VHDL. One is FOR generate and other is IF generate. They can be used to replicate a structure or logic and to enable/disable a block. FOR can be used for iterative elaboration of a logic and IF can be used for conditional elaboration of some block.

3. A generate statement is generally associated with ________ modeling.
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and data flow
Answer: c
Clarification: A generate statement is usually associated with component instantiation which is a part of structural modeling. For example, the FOR generate can be used to instantiate arrays of components and similarly IF can be used to instantiate the component conditionally.

4. What is the correct syntax for FOR generate statement?
a)

label : FOR parameter IN range GENERATE
      begin
      declarations;
      concurrent statement
      END GENERATE label;

b)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      concurrent statement
      END GENERATE label;

c)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END GENERATE label;

d)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END label GENERATE;

View Answer

Answer: b
Clarification: For defining a generate statement the for loop is used in conjunction with GENERATE keyword. The local declarations can be made inside a generate block. Please note that generate is a concurrent statement which can contain concurrent statements only.

5. Using a label is compulsory with a GENERATE statement.
a) True
b) False
Answer: a
Clarification: Unlike other statements of VHDL, using a label is compulsory in a GENERATE statement. This label should be unique for each different GENERATE. Moreover, this label can be used to end the generate statement as well.

6. Which of the following is a correct statement for IF generate statement?
a)

     IF condition GENERATE
     begin
     declarations;
     concurrent_statements;
     END GENERATE label;

b)

     label : IF condition GENERATE
     declarations;
     begin
     sequential_statements;
     END GENERATE label;

c)

     IF condition GENERATE
     declarations;
     begin
     sequential_stataements;
     END GENERATE label;

d)

     label : IF condition GENERATE
     declarations;
     begin
     concurrent_statements;
     END GENERATE label;

View Answer

Answer: d
Clarification: A label is compulsory with IF generate statement as well. However, IF is a sequential statement, but when used with GENERATE it includes concurrent statements. The declarative part and the staements part is separated by the keyword BEGIN.

7. FOR generate creates ____________ objects.
a) Dissimilar
b) Unique
c) Different
d) Similar
Answer: d
Clarification: The generate statement will instance an array of objects which are all of homogeneous type or similar. This allows to generate multiple objects with a single statement.

8. What is realized in the code given below?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_logic IS
GENERIC n : INTEGER := 8;
PORT (sig1 : bit_vector(n-1 DOWNTO 0);
             Sig2 : bit_vector(n-1 DOWNTO 0));
END my_logic;
ARCHITECTURE test OF my_logic IS
COMPONENT or2
   PORT(a0, a1 : IN BIT;
                z         : OUT BIT);
END COMPONENT or
BEGIN
ORARRAY : FOR i IN (n-1) DOWNTO 0 GENERATE
                   or_gate : or2
PORT MAP ( a0 => sig1(i),
                       A1 => sig2(i),
                         z => y(i));
END GENERATE ORARRAY;
END test;

a) 7- Bit parallel adder ignoring the carry
b) 7- Bit parallel adder including the carry
c) 8- Bit parallel adder ignoring the carry
d) 8- bit parallel adder including the carry
Answer: c
Clarification: Since, a generic is used to specify the length of the arry which is assigned a value 8. The loop iterates from 7 downto 0 that means 8 times. So, an array of OR gates is instantiated by using this code including 8 OR gates. So, it is 8 bit parallel adder ignoring the carry.

9. Which of the following is legal?
a)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     concurrent_statement; 
      END GENERATE;

b)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     declarations;     
      concurrent_statement; 
      END GENERATE;

c)

    label : FOR n IN 7 DOWNTO 0 GENERATE
     begin
     declarations; 
     concurrent_statement; 
      END GENERATE;

d)

    label : FOR n IN 7 DOWNTO 0 GENERATE
    begin 
    concurrent_statement; 
     END GENERATE label;

View Answer

Answer: a
Clarification: If the generate statement has no local declaration which means it has only statement part then there is no need to use the BEGIN keyword. Also, label is compulsory for a generate statement but it is not mandatory to use a label at the end of the generate statement.

10. Generate statements can’t be nested.
a) True
b) False
Answer: b
Clarification: It is possible to nest multiple generate statements means we can use one generate statement inside another generate statement. This can be useful to generate to dimensional or multi-dimensional arrays.

11. Which of the following is not possible to use inside the FOR generate statement?
a) IF
b) IN
c) EXIT
d) PORT MAP
Answer: c
Clarification: It is not possible to terminate the loop early in the case of generate statement. So, no such statement can be used inside the loop which can cause it to terminate early. Therefore, such statements like EXIT, BREAK etc. can’t be used.

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This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Designing Moore Type FSM with VHDL”.

1. Output values of Moore type FSM are determined by its ________
a) Input values
b) Output values
c) Clock input
d) Current state
Answer: d
Clarification: The output values of a Moore type FSM are determined only by its current state. The output is computed by the state outputs which serve as the input in the flip-flop. The output changes synchronously with the clock edge and state transition.

2. Moore machine output is synchronous.
a) True
b) False
Answer: a
Clarification: Output of the Moore type FSM are synchronous, it works with respect to the clock and change only with the state transition. Mealy type FSM gives asynchronous output.

3. Finite state machines are combinational logic systems.
a) True
b) False
Answer: b
Clarification: Finite state machines are SEQUENTIAL logic systems. In sequential logic systems, the output depends on the inputs and also on the present state of the system. It consists of a set of states, set of rules for moving from state to state, inputs and outputs.

4. What happens if the input is high in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: a
Clarification: The system changes the state as long the input is high. The system also has an output which is 1 if the input is high since there is a change in state which leads to the output.

5. What happens if the input is low in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: b
Clarification: There is no transition in the state if the input is low. If the system is in a particular state, it remains in that state only until the input becomes high. The system also has an output which is 0 if the input is low since there is no change in the state, it doesn’t reach the output state.

6. In FSM diagram what does circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: b
Clarification: In FSM diagram circle represent the states. For example: Assume there are four states in an FSM i.e. A, B, C and D. The encircled one out of the four will represent the state. If B is encircled, it shows FSM is in state B.

7. In the FSM diagram, what does arrow between the circles represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: a
Clarification: In the FSM diagram, arrows between the circles represent the change of one state to another state. For example: Assume there are four states in an FSM i.e. A, B, C and D. The arrow between the states A and B show the transition of state from A to B.

8. In the FSM diagram, what does the information below the line in the circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: c
Clarification: In the FSM diagram the information below the line in the circle represents the output value when in each state. It is represented by 1 and 0. If there is a state change then 1, otherwise 0.

9. Moore machine has _________ states than a mealy machine.
a) Fewer
b) More
c) Equal
d) Negligible
Answer: b
Clarification: In Moore type FSM, more logic is required to decipher the outputs which result in more circuit delays. Moore machines generally respond one clock cycle later while mealy machines respond in the same clock cycle. That is why Moore machines require more states.

10. State transition happens _______ in every clock cycle.
a) Once
b) Twice
c) Thrice
d) Four times
Answer: a
Clarification: Every arrow shows a transition from one state to another, transition of state happens once in one clock cycle. Depending on the present input, it may go to a different state every time so there is a change of state only one time.

This set of VHDL Questions on “Need of HDLs”.

1. In what aspect, HDLs differ from other computer programming languages?
a) No aspect; both are same
b) HDLs describe hardware rather than executing a program on a computer
c) HDLs describe software and not hardware
d) Other computer programming languages have more complexity
Answer: b
Clarification: HDLs (Hardware Description Languages) are used to describe hardware for any electronic circuit or system; whereas other computer programming languages execute a program on the computer itself.

2. Which of the following HDLs are IEEE standards?
a) VHDL and Verilog
b) C and C++
c) Altera and Xilinx
d) Quartus II and MaxPlus II
Answer: a
Clarification: VHDL and Verilog are the only two HDLs endorsed by IEEE. C andC++ are not HDLs. Altera and Xilinx are devices on which these HDLs can be used. Quartus II and MaxPlus II are the platforms for simulation of hardware described by HDLs.

3. Why we needed HDLs while having many traditional Programming languages?
a) Traditional programming languages are complex
b) HDLs are complementary to traditional programming languages to complete the design process
c) Some characteristics of digital hardware couldn’t be captured by traditional languages
d) HDLs offer more complexity than traditional programming languages.
Answer: c
Clarification: Digital systems are very complex and this complexity is increasing day by day. Some characteristics like propagation delay, concurrent processing and interconnection of parts can’t be captured with traditional languages.

4. An HDL can’t describe Hardware at Gate level as well as switch level?
a) True
b) False
Answer: b
Clarification: An HDL supports the hierarchical design process. It can describe the circuit or hardware at every possible level, whether it is gate level or switch level or RTL level.

5. Why do we need concurrent processing for describing digital systems in HDLs?
a) Faster processing than conventional programming languages
b) Concurrent processing is easier than sequential processing
c) It allows taking timing constraints into consideration
d) Complexity of digital systems needs concurrent processing
Answer: d
Clarification: Due to the complexity of digital circuits, we need to process all the instructions at the same time. For example, current can flow in the two branches at the same time which can affect the output of the system, if sequentially processed.

6. An ASIC can be correctly designed by using programming languages like C or Assembly.
a) True
b) False
Answer: b
Clarification: By using HDL, we specify what we need. We can optimize the circuit by using HDLs. ASIC(Application Specific IC) is a very complex which may consist of millions of transistors. So, we need concurrent execution first of all. Apart from that, we need timing information and other complex features of the digital system too.

7. VHDL is based on which of the following programming languages?
a) ADA programming language
b) C
c) Assembly
d) PHP
Answer: a
Clarification: The syntax and whole structure of VHDL code is based upon ADA programming language whereas Verilog HDL finds its origin from C language.

8. What is the advantage of using VHDL instead of any other HDL?
a) Week typing
b) Based on ADA
c) Portability
d) Easy to code
Answer: c
Clarification: A circuit specified in VHDL can be implemented in different chips and is compatible with CAD tools provided by all companies. Therefore, without any modification, we can use VHDL code anywhere. This is the biggest advantage because digital circuit technology changes rapidly.

9. Which of the following is a characteristic of VHDL?
a) Case sensitive
b) Use of simple data types
c) Based on C programming language
d) Strongly typed language
Answer: d
Clarification: VHDL is a strongly typed language i.e. we have to write a long code to define operations.

10. Which of the following is a characteristic of Verilog HDL?
a) Strongly typed language
b) Case sensitive
c) Better library
d) Not portable
Answer: b
Clarification: Verilog HDL is a case sensitive language which means ‘a’ and ‘A’ means different if you are coding in Verilog.

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This set of VHDL Questions and Answers for Freshers on “Types of VHDL Modelling”.

1. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
Answer: b
Clarification: Modeling refers to the descriptive style we are using to describe our digital system. Modeling type is the type of statement used in architecture block to describe a specific system or circuit. It may define a structure or behavior or anything else.

2. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
Answer: d
Clarification: VHDL modeling is of three types. These types are behavioral modeling, dataflow modeling and structural modeling. There is no such modeling called component modeling. However, one can declare components in structural modeling.

3. In behavioral modeling, what do descriptive statements describe?
a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution
Answer: a
Clarification: Behavioral style specifies what a particular system does in a program. It gives the details of output values corresponding to the set of input values. In general, behavioral modeling use processes to describe the functioning of system, but no detail is provided regarding the design of the system.

4. Which of the following statement is used in structural modeling?
a) portmap()
b) process()
c) if-else
d) case
Answer: a
Clarification: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap() function is used to map the specific component in the design.

5. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow
Answer: c
Clarification: The primary unit of a behavior description in VHDL is process which describes the behavior of system on various combinations of inputs. All the system is described by using processes and therefore, process is the basic unit.

6. Which of the following modeling style follows the sequential processing of instructions?
a) Dataflow modeling
b) Behavior modeling
c) Structural modeling
d) Component modeling
Answer: b
Clarification: Behavior modeling uses sequential processing whereas dataflow and structural modeling uses concurrent statements. In sequential statements, the instructions are executed one after another whereas concurrent statements are executed simultaneously.

7. __________ modeling uses logic gates and basic blocks to describe the functionality of system.
a) Behavioral
b) Structural
c) Dataflow
d) Component
Answer: c
Clarification: In dataflow modeling, the system is represented as flow of control and movement of data. It describes how data flows from input to output by using primitive logic functions. Unlike behavioral modeling, it uses concurrent statements and logic functions.

8. Structural style use processes.
a) True
b) False
Answer: b
Clarification: Structural style does not use processes since it just describe the graphical representation of system. It doesn’t need process statements. Process statements are required to describe the behavior and not structure. Therefore, structural doesn’t need processes.

9. Component instantiation is the part of __________ modeling.
a) Behavior
b) Component
c) Dataflow
d) Structural
Answer: d
Clarification: Component declaration and component instantiation is a part of structural modeling. It first declares the component and then instantiation takes place by using portmap function. Structural modeling is based on netlist.

10. Which of the following architecture defines the data flow modeling of ‘and’ gate?
a)

ARCHITECTURE and_1 OF and_gate IS
    begin
    y <= a AND b;
    end and_1;

b)

ARCHITECTURE dataflow OF and_gate IS
    Process(a, b, y);
    begin
    y <= a AND b;
    end dataflow;

c)

ARCHITECTURE and_1 OF and_gate IS
    begin
    IF(a = ‘1’ and b = ‘1’) THEN
    c <= 1;
    ELSE c &lt;= ‘0’;
    end and_1;

d)

ARCHITECTURE dataflow OF and_gate IS
    begin
    y <= a AND b;
    end and_1;

View Answer

Answer: a
Clarification: Dataflow uses primitive and basic functions to describe the flow of data through registers from inputs to output. It uses concurrent statements and process() is a sequential statement which can’t be used in data flow modeling. It is not necessary to write the name of ARCHITECTURE as ‘dataflow’.

11. Refer to the code given below, which type of modeling is used to describe the system?

ARCHITECTURE and_1 OF and_gate IS
begin
process(a, b, y)
begin
IF(a = ‘1’ and b = ‘1’) THEN
y <= ‘1’;
ELSE y <=’0’;
end IF;
END process;
END and_1;

a) Structural
b) Component
c) Dataflow
d) Behavioral
Answer: d
Clarification: Above shown code is for AND gate and it is using process statement. The code gives information about output values for different combinations of input values. Therefore, the code given is behavioral style of modeling.

12. Which logic function is described in the code given below?

ARCHITECTURE my_func OF my_logic IS
begin
process(a, b, y)
begin
IF(a = ‘0’ and b = ‘0’) THEN
y <= ‘0’;
ELSIF (a = ‘1’ and b= ‘1’) THEN
y<= ‘0’;
ELSE y <= ‘1’;
END if;
END process;
END my_func;

a) AND
b) EXOR
c) OR
d) EXNOR
Answer: b
Clarification: The modeling shown is behavioral modeling. The output y is low for 00 and 11 else the output is high. Therefore, the given logic is for exclusive OR gate. Since in EXOR he output is high for 01 and 10 which is shown in the code given.

13. Which modeling style does the following code represents?

Architecture my_logic OF logic_func IS
Component gate_1
PORT (b1, b2 : IN BIT;
s : OUT BIT);
END component;
Component gate_2 IS
PORT (b1,b2 : IN BIT;
C : OUT BIT);
END component;
SIGNAL a, b, sum, carry : BIT;
begin
EXOR : gate_1 portmap (a, b, sum);
AND : gate_2 portmap (a,b ,carry);
END my_logic

a) Structural
b) Component
c) Behavior
d) Dataflow
Answer: a
Clarification: The code describes the every component present in the circuit, here gate_1 and gate_2 are two components and then it describes the inputs and outputs of the gates by using portmap function. In this way structural modeling describes all the functions and their interconnection. Moreover, it uses concurrent statements.

14. Ports are known as _________ to the component.
a) Structure
b) Behavior
c) Function
d) Interface
Answer: d
Clarification: Ports are used to declare the inputs and outputs of a specific component in the structural modeling. They act as an external interface of the component since it tells the number of input and outputs a component can have.

15. What is the use of a function called port map()?
a) Component declaration
b) Defining identifiers
c) Component instantiation
d) Defining inputs and outputs
Answer: c
Clarification: The function portmap() is used for component instantiation. By taking instances of input output ports declared at the time of declaration, the component is instantiated. Basically, to define the relation of component with the signals, we use portmap().

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