Category: VHDL Objective Questions

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Process Statement – 1”.

1. Process is a _______ statement.
a) Concurrent
b) Sequential
c) Delay
d) Both concurrent and sequential
Answer: a
Clarification: Process statement itself is a concurrent statement. Since, the architecture of an entity can contain only concurrent statements, so, process is a concurrent statement. Basically, Process itself is a concurrent statement which includes sequential statement. The statements enclosed in a process statement are executed sequentially.

2. If there is more than one process in a VHDL code, How they are executed?
a) One after the other
b) Concurrently
c) According to sensitivity list
d) Sequentially
Answer: b
Clarification: All the processes in a design execute concurrently or in a parallel manner. However, at a given time, only one statement is executed within the process. More than one processes can execute in a parallel manner, but the same is not true for statements within a process.

3. A process has a declaration part.
a) True
b) False
Answer: a
Clarification: A process can have a declaration part followed by statement part. A process can have its local variables, constants, types or subtypes declared in it which will be visible to the process only. The local process variables can’t be used outside the process.

4. Local variables in a process can be declared __________
a) Anywhere within the process
b) After a sequential statement
c) Before the BEGIN keyword
d) After the BEGIN keyword
Answer: c
Clarification: BGIN keyword specifies the start of sequential statements. The process declaration part is an optional part and the variables must be defined before the BEGIN keyword. No declaration is allowed after the keyword BEGIN.

5. Which of the following is correct syntax for process declaration?
a)

     {Label :} PROCESS
     {process_declaration_part};
      sensitivity_list;
     BEGIN
     sequential_statements;
     END PROCESS {Label};

b)

     PROCESS {sensitivity_list}
     {process_declaration_part}
     BEGIN
     sequential_statements;
     END PROCESS {Label};

c)

     {Label :} PROCESS
     {process_declaration_part}
     BEGIN
     sensitivity_list;
     sequential_statements;
     END PROCESS;

d)

     {Label :} PROCESS {sensitivity_list}
     {process_declaration_part}
     BEGIN
     sequential_statements;
     END PROCESS {Label};

View Answer

Answer: d
Clarification: A process is declared by using an optional label followed by keyword process and the list of signals to which process is sensitive. After which, there is a declaration part for the process and a statements section. Both parts are separated by keyword BEGIN. THEN, the process is terminated by using keyword END followed by Process.

6. Sensitivity list of a process contains __________
a) Constants
b) Signals
c) Variables
d) Literals
Answer: b
Clarification: A process has its sensitivity list containing the names of signals to which the process is sensitive. It can contain any number of signals which will trigger the process of change of value of any of these signals. It may not contain constants or variables, only signals are valid.

7. Which of the following statement is used when there are no signals in the sensitive list?
a) WHEN
b) IF ELSE
c) WAIT
d) CASE
Answer: c
Clarification: A process can be sensitive to one or more signals. These signals are either specified in the sensitivity list of the process. If there is no sensitivity list, then the signals used in WAIT statements are the signals to which process is sensitive.

8. What is the effect of the sensitivity list on the process?
a) Process executes when any of the signal in sensitivity list changes
b) Process executes sequentially when sensitivity list is specified
c) If there is no sensitivity list, then the process will not execute
d) Helps in simulation
Answer: a
Clarification: The sensitivity list contains those signals which affect the execution of the process. Whenever one or more statements inside the sensitivity list changes, the execution starts. So, the process is executed again and again whenever any value change. It starts from BEGIN keyword and all statements are executed serially and then it waits for change in any value.

9. It is mandatory to use a label for any process.
a) True
b) False
Answer: b
Clarification: The use of label is optional. The purpose of using label is just to improve the readability of code. If it is used, then at the end of the process the same label should be written. For example, if label L1 is used to start the process then at the end, it must be- END PROCESS L1.

10. If no signal in the sensitivity list is changed, then how many times the process will be executed?
a) 3
b) 2
c) 1
d) 0
Answer: c
Clarification: The process is executed at least once, no matter if the signal changes or not. At the time when the simulation is initiated, the process is triggered. After this one time execution of process, it waits for change in state of signals in sensitivity list.

11. Which of the following statements can be seen as sequential equivalent to the selected concurrent assignment?
a) IF ELSE
b) WAIT
c) WHEN
d) CASE
Answer: d
Clarification: The selected assignment is a concurrent statement and therefore, can’t be used inside a process. CASE statement is a sequential statement which can be seen as an equivalent to the selected assignment which chooses one of the n different signals or variables.

12. A __________ can’t be declared inside a process.
a) Signal
b) Variable
c) Constants
d) Subprograms
Answer: a
Clarification: The process has a declaration part in which everything can be declared except a signal. The variables, constants, types, subprograms can be declared in the process and the scope for variables declared in the process is local to the process itself.

This set of VHDL Questions and Answers for Entrance exams on “Functions and Subprograms – 2”.

1. Refer to the function defined below, a and b have respectively following data objects.

FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR; b : STD_LOGIC) RETURN BOOLEAN IS
…..;

a) Constant, Constant
b) Constant, Signal
c) Signal, Constant
d) Signal, Signal
Answer: c
Clarification: Until the data object is not specified, the corresponding must be considered as a constant. In the above function, a is specified as a signal but b is not specified therefore, b is taken as a constant. So, a is a signal as specified and b is a constant.

2. What should be the mode of signal a in the following function definition?

FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR) RETURN INTEGER IS
…..;

a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: a
Clarification: The default and only signal mode which is applicable to a parameter of the function is the IN mode. There is no need to specify the mode at the time of definition. It is obvious that the mode is taken as IN mode. No other mode can be used in the parameter of a function.

3. Functions are called using ______ no of ________ statement(s).
a) 1, If
b) 1, Assignment
c) 2, If
d) 2, Assignment
Answer: b
Clarification: The functions are called using a single assignment statement. A function is always invoked as an expression and therefore, it is called by using an assignment statement in which function appears on the right side of the assignment operator.

4. Which of the following type can’t be a parameter of a function?
a) Signals
b) Constants
c) Files
d) Variables
Answer: d
Clarification: Apart from signals and variables, the files can also be used as a parameter to a function. The only restriction is to use a variable in the parameter of the function. One may use signal of IN mode, any constants and files in the parameter list.

5. A component may be declared and instantiated inside a function.
a) True
b) False
Answer: b
Clarification: In the declaration part of a function, one may declare a variable. But the declaration of a signal and a constant is not allowed inside a function. The constant instantiation is a concurrent statement and a function consists of sequential statements. Therefore, it is not possible to declare and instantiate a component.

6. What is the use of resolution functions?
a) Return the value of a signal with multiple drivers
b) Resolve value of a constant with multiple drivers
c) Convert one data type into another
d) Convert one data object into another
Answer: a
Clarification: Resolution function is used to resolve the value of a signal when the signal is driven by multiple drivers. It returns the new value of the signal by resolving all the drivers to give a single new value.

7. It is not possible to use multiple driver signals without a resolution function.
a) True
b) False
Answer: a
Clarification: In VHDL, it is illegal to have a signal with multiple drivers without a resolution function attached to the signal. Most of the resolution functions are predefined in the packages provided by STD and IEEE. But, if there is no resolution function then we can’t assign multiple values to the signal.

8. A resolution function is invoked when ________
a) The signal is assigned multiple values
b) All the drivers has changed their value for once at least
c) Any of the driver changes its value
d) The signal is assigned a second value
Answer: b
Clarification: A resolution function is called whenever one of the drivers for the signal has an event occurred on it. The resolution function is then executed and it returns a single value from all the driver values, that value is the new value of the signal.

9. How many parameters are there in a resolution function?
a) 3
b) 2
c) 0
d) 1
Answer: d
Clarification: A resolution function has one parameter or argument and returns a single value. The parameter is of array(unconstrained) type having the values of all the drivers attached to the signal.

10. What would be the length of array used as a parameter to the resolution function which resolves the value of a signal having 2 drivers?
a) 1
b) 2
c) 3
d) Infinite
Answer: b
Clarification: Though the array is unconstrained, but when the number of drivers is known, then the length is limited to the same number. For example, if there are two drivers for a signal, then the array used as a parameter must be of length two.

VHDL for Entrance exams, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Flattening and Factoring of Functions”.

1. What is the process of flattening?
a) Converting an optimized function to unoptimized form
b) Converting a Boolean function to PAL format
c) Converting a Boolean function to PLA format
d) Converting a Boolean function to POS form
Answer: c
Clarification: Flattening is a process of converting the unoptimized Boolean description into a PLA format. PLA format is a format in which the description is converted into sum of products form i.e. in the form of OR and AND arrays.

2. Flattening creates a flat signal representation of ______ levels.
a) 1
b) 2
c) 3
d) 4
Answer: b
Clarification: Flattening is named so because it creates a flat signal representation of only two levels: an AND level and an OR level. Because it converts the function into PLA form in which we can implement only sum of products.

3. How will you flatten the following function?

a = b AND c;
b = x OR (y AND z);
c = q OR w;

a) a = (x AND q) OR (q AND y AND z) OR (w AND x) OR (w AND y AND z);
b) a = (x OR q) AND (q OR y OR z) AND (w OR x) AND (w OR y OR z);
c) a = (x AND b) OR (c AND y AND z) OR (c AND x) OR (b AND y AND z);
d) a = (w AND q) OR (w AND y AND z) OR (q AND x) OR (q AND y AND z);
Answer: a
Clarification: Flattening means only two levels which are AND and OR arrays. So, there must be no intermediate levels. For example, in the question given above, b and c are two intermediate signals used. So, first b and c must be solved then only a can be solved. Therefore, flattening will give the resultant shown in option a. It is Boolean equivalent of the first without any intermediate node.

4. What is the result of flattening of functions?
a) Increased readability
b) Increased speed
c) Decreased speed
d) Decreased readability
Answer: b
Clarification: Flattening of functions increase the speed of functions. Since there are no intermediate nodes, there are few logic levels from the input to the output. It is only good for smaller functions in which numbers of terms are not more.

5. In which of the following functions, the flattening is difficult?
a) Functions containing many XOR
b) Functions which are already minimal
c) Functions which are slow due to intermediate nodes
d) Functions which is always false
Answer: a
Clarification: In case, when a function has many numbers of terms, especially with XOR functions. Because a n- input EXOR gate needs 2^(n-1) terms. Due to which it becomes much complicated to convert that particular function into flattened PLA form. Due to this reason the speed decreases.

6. Which of the following is the opposite of flattening of functions?
a) Structure
b) Adding intermediate nodes
c) Un-flattening
d) Factoring
Answer: d
Clarification: Factoring is the process of adding intermediate terms or nodes to add structure to a description. So, factoring is exactly opposite of flattening in which the intermediate nodes are removed and made a single PLA function.

7. The main advantage of using factoring is ________
a) Reducing the speed
b) Reducing the number of terms
c) Adding intermediate nodes
d) Reducing flattening
Answer: b
Clarification: The main disadvantage of flattening is that it confuses the whole function by adding more number of terms in one expression which decreases the speed. To overcome this disadvantage, factoring is used to reduce the number of terms in the expression.

8. What is another name for the factoring of functions?
a) De-flattening
b) Intermediation
c) Structuring
d) De-structuring
Answer: c
Clarification: Factoring is also known as structuring. This is the name given to factoring because it structures the expressions and increases their readability. It basically uses the concept of factoring used in mathematics to do so.

9. Which factor can be there in the following two functions?

x = a AND b OR a AND c;
y = b OR c OR d

a) a AND b
b) b OR a
c) b AND c
d) b OR c
Answer: d
Clarification: After factoring, using various Boolean properties, the term b or c can be factored out to a separate intermediate node. In the first expression, if we see it is equivalent to a AND (b or c). Also, b OR c is a part of second expression as well.

10. What would be the ideal case for a design?
a) Using factoring only
b) Using flattening only
c) Using both flattening and factoring
d) Neither using flattening and nor factoring
Answer: c
Clarification: Since factoring will add an intermediate node which can reduce speed. On the other hand, the flattening process will increase the speed. But, at the same time flattening can increase the area and decrease the fan-out. This is completely opposite to factoring which reduces the area and increases the fan-out.

This set of VHDL Interview Questions and Answers on “Data Objects and Types”.

1. SIGNED and UNSIGNED data types are defined in which package?
a) std_logic_1164 package
b) std_logic package
c) std_logic_arith package
d) standard package
Answer: c
Clarification: SIGNED and UNSIGNED data types are defined in the std_logic_arith package of the IEEE library. These data types are mainly intended for arithmetic operations. This is why they are defined in the arithmetic package.

2. What is the correct method to declare a SIGNED type signal ‘x’?
a) SIGNAL x : IN SIGNED
b) SIGNAL x : IN SIGNED
c) SIGNAL x : IN SIGNED (7 DOWNTO 0)
d) SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0)
Answer: c
Clarification: Unlike BIT and STD_LOGIC types; SIGNED and UNSIGNED follow the syntax similar to BIT_VECTOR and STD_LOGIC_VECTOR. Also, IN and OUT are just to specify the direction of signal.

3. An UNSIGNED type is always greater than zero.
a) True
b) False
Answer: a
Clarification: In SIGNED and UNSIGNED, SIGN word refers to the positive or negative sign of any number. UNSIGNED data type has no sign and therefore, it is always positive. Therefore, an UNSIGNED number will be always greater than zero.

4. What will be the value of x in the following code?

SIGNAL x : IN UNSIGNED (3 DOWNTO 0 );
x <= “1101”;

a) 12
b) 5
c) -5
d) 14
Answer: d
Clarification: x is declared as an UNSIGNED data type. Therefore, all the 4 bits will be data bits and it will be positive. So, converting 1101 in decimal, we get 1101 equivalent to 14 in decimal number system.

5. What is the decimal equivalent of x in the following code?

SIGNAL x : OUT SIGNED (3 DOWNTO 0 );
x <= “1101”;

a) -5
b) 5
c) -3
d) -14
Answer: c
Clarification: Signed numbers always have first bit representing the sign of the number which is one for the negative and zero for the positive. Also, signed number is represented in 2’s complement form. Therefore, the given number is -3.

6. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?
a) x <= a + b; y <= a – b;
b) x <= a OR b; y <= a AND b;
c) x <= a + b; y <= a OR b;
d) x <= a OR b; y <= a + b;
Answer: a
Clarification: SIGNED and UNSIGNED data types are intended for arithmetic operations mainly and using logical operators with these data types is illegal. Therefore, only option x <= a + b; y <= a – b; is completely legal. In all other options there are logical operations so those can’t be considered as legal.

7. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?
a) x <= a.b
b) x <= a OR b
c) x <= a + b
d) x <= a && b
Answer: b
Clarification: Unlike SIGNED and UNSIGNED, STD_LOGIC_VECTOR data type is used mainly for logical operations and we can’t use arithmetic operations with STD_LOGIC_VECTOR. Also, && is not the sign for any operation in VHDL, if you want to perform and operation, then you have to write AND not &&.

8. What do we call the data type used for representing distance, current, voltage, time, etc?
a) Integer
b) Real
c) Physical
d) Imaginary
Answer: c
Clarification: Physical type is used for representing physical values such as time, voltage, etc. by using some base unit. Physical quantities are used in various digital systems and these are important for modelling such systems. Integer and Real are the data types for numbers and there is no data type called Imaginary.

9. What is the meaning of the base unit?
a) Smallest possible unit of any physical literal
b) SI unit of any physical literal
c) CGS unit for any physical literal
d) Fundamental building block of any design
Answer: a
Clarification: Base unit is the smallest possible unit for any physical literal by using which we can derive all other units of the same literal. For example, in case of TIME, the base unit is nanosecond. We can create any bigger unit by using nanoseconds. For example 1 microsecond = 1000 nanosecond.

10. Which of the following is only predefined physical literal in VHDL?
a) VOLTAGE
b) TIME
c) CURRENT
d) DISTANCE
Answer: b
Clarification: TIME is the only predefined physical data type in VHDL. The base unit of TIME is nanosecond. TIME literal is defined in the standard package of std library.

11. SIGNAL a : REAL; which of the following is illegal assignment for a?
a) a <= 1.8
b) a <= 1.0 E10
c) a <= 1.0 E-10
d) a <=1.0 ns
Answer: d
Clarification: Units nanosecond (ns) written after the number shows that it is of type TIME and VHDL doesn’t allow TIME type to be assigned to a real Signal. So option d is illegal.

12. Multidimensional arrays can be used for the implementation of memories.
a) True.
b) False.
Answer: a
Clarification: Multidimensional arrays can be seen as array of arrays. For example, we need to implement ROM of 512×4 then we need to define a 2 dimensional array with 4 columns and 512 rows. So, memories can be defined by using 2D array. In which one dimension can show the size of memory and another can show the width of one word.

13. RECORD in VHDL is similar to________ in C.
a) Array
b) File
c) Structure
d) Pointer
Answer: c
Clarification: As in C, Structures are used to collect different data types under a common name. Similarly, RECORD type in VHDL is used for collecting different data types and objects in a single object.

14. What is the difference between SIGNAL and VARIABLE?
a) The value of SIGNAL never varies whereas VARIABLE can change its value
b) SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
c) SIGNAL depends upon VARIABLE for various operations
d) SIGNAL is global and VARIABLE is local to the process in which it is declared
Answer: d
Clarification: SIGNALs are used to pass information between entities, they act as interconnection between different entities whereas VARIABLEs can be used in the process or subprogram in which it is declared. So, VARIABLEs are local to the block in which they are declared.

15. Access types are similar to _________ in traditional programming languages.
a) Pointers
b) Arrays
c) Structures
d) Files
Answer: a
Clarification: Access types are used to hold an address of some object which is quite similar to pointers in traditional programming languages. By using the address stored in Access data type, we can access another data objects similar to pointers.

VHDL for Interviews, .

This set of VHDL Quiz on “Process Statement – 2”.

1. It is possible to use sensitivity list and wait statements in the same process.
a) True
b) False
Answer: b
Clarification: The sensitivity list and wait statements can’t be used simultaneously in the same process. One can either use sensitive list or wait statements in a process. Both of them are used to define the signals to which the process is sensitive. These sensitive signals execute process as an infinite loop.

2. The process can be __________ by using WAIT statements.
a) Suspended
b) Resumed
c) Suspended as well as resumed
d) Cannot be determined
Answer: c
Clarification: The signals used in WAIT statements are the statements which can also be declared in sensitivity list. These signals can be used to suspend as well as resume the process as many times as designer want.

3. A postponed process runs when ___________
a) All the other processes have completed
b) After completion of one particular process
c) Concurrently with all other processes
d) First of all processes
Answer: a
Clarification: A postponed process can be defined in VHDL-93. A postponed process runs when all the normal processes have completed at a particular point of time at the time of simulation. These processes can’t schedule any further events with zero delays.

4. Which of the following statement can’t be used inside a process?
a) WAIT
b) IF ELSE
c) Variable declaration
d) PORT MAP
Answer: d
Clarification: A process itself is a concurrent statement which can have only sequential statements. IF ELSE and WAIT statements can be easily used inside a process. Also, there is a declaration part of the process so variable declaration is possible. Only PORT MAP is not possible inside the process among the above options since it is a concurrent statement.

5. Which of the following signal cause the process to execute?

PROCESS (clr)
BEGIN
IF (clr = ‘1’) THEN
y <= ‘0’;
ELSE
y <= input;
END PROCESS;

a) input
b) y
c) clr
d) x
Answer: c
Clarification: The sensitivity list of the process contains only one signal which is ‘clr’. So, the process will be executed when the value of clr changes. Though value of input will be assigned to y once but change in value of ‘input’ will not cause execution of process again.

6. The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles (starting from the beginning) will be taken to change the initial value of z, refer to the process given below?

PROCESS (y)
BEGIN
x <=y;
z <= NOT y;
END PROCESS

a) 1
b) 2
c) 3
d) 4
Answer: b
Clarification: At the very beginning, the value of z is 0. After 1 delta cycle, the value of y changes which causes process to run again. So, in 2nd delta cycle process will be executed but assignments will be done after the execution of process is over. So, at the end of 2nd delta cycle, the assignments will be executed.

7. A combinational process must have all the _________ signals in its sensitivity list.
a) Input
b) Output
c) Declared
d) Used
Answer: a
Clarification: All the inputs must be used in the sensitivity list to get the desired list. Because if any of the input signal is updated then it is needed that the output also gets updated. To update any output, one needs to activate the process again which is possible only by the signals in the sensitivity list. Therefore, all the signals which it has to read or the input signals must be used in the sensitivity list.

8. There is no restriction on the number of wait statements inside a process.
a) True
b) False
Answer: a
Clarification: A process can have multiple WAIT statements and can be placed anywhere inside the process body. However, it can have only one sensitivity list (can contain many signals) but, there is no restriction on use of WAIT statements.

9. Which of the following circuit can’t be described without using a process statement?
a) Multiplexer
b) D flip-flop
c) Decoder
d) Comparator
Answer: b
Clarification: Since a flip flop requires a clock signal which can’t be used directly in architecture without using a process (as it is a sequential process). So, for using the clock, using a process is mandatory. All the other circuits like multiplexer, decoder or comparator are combinational circuits and do not need any clock. So, they can be modeled without using a process.

10. Which of the following signal uses keyword EVENT?
a) Variables
b) Output
c) Input
d) Clock
Answer: d
Clarification: To use a clock signal in a design description, EVENT is used. It is used inside the process body which indicates the change in value of clock signal so that the design can be synchronized with the clock signal or clock frequency. It can be used in an IF statement to assign any input expression to the output.

11. Refer to the code given below, what kind of circuit is designed?

SIGNAL x : IN BIT;
SIGNAL y : OUT BIT;
SIGNAL clk : IN BIT;
PROCESS (clk)
BEGIN
IF (clk’EVENT and clk = ‘1’)
y ;&lt= x;
END PROCESS

a) Buffer
b) Latch
c) Flip flop
d) Shift Register
Answer: c
Clarification: It is clear from the code that it is a sequential circuit using clock EVENT and the value of input is assigned to the output directly. So, it can’t be a buffer since buffer doesn’t need any clock signal. So, It is a synchronized flip flop. Clearly, It can be said that the given flip flop is a D flip flop.

12. The driver(s) of signal y is _________

PROCESS ()
BEGIN
y <= ‘1’;
y <= x;
y <= z;
END PROCESS;

a) z
b) x
c) x and z
d) 1
Answer: a
Clarification: Since the assignment statements are appearing inside a process. Therefore, they are sequential assignment statement. A signal being assigned a value inside a process can’t have multiple drivers. It can have only one driver since only last statement is taken into consideration. So, the signal y is driven by signal z.

13. The resolution function is needed to resolve the value of _______

PROCESS ()
BEGIN
y <= x;
y <= z;
END PROCESS;

a) z
b) y
c) x
d) No x, y and z
Answer: d
Clarification: Since these assignments are appearing inside a process so no signal can have more than one driver. A resolution function is needed only if the signal has multiple drivers. However, if these statements were used outside the process, then the resolution function was required to resolve the value of y.

VHDL for Quizzes, .

This set of VHDL Questions and Answers for Campus interviews on “Functions and Subprograms – 3”.

1. In VHDL it is not possible to use recursive functions.
a) True
b) False
Answer: b
Clarification: Like all other traditional programming languages, in VHDL too we can use recursive functions. Recursive function is the function which calls itself again and again until a condition comes to be true. It is possible to call functions recursively.

2. Apart from using WAIT statements, which of the following is not possible in functions?
a) Variable assignment
b) Return statement
c) Variable declaration
d) Signal assignment
Answer: d
Clarification: The signal assignment can’t be done inside a function body. It is possible to declare a variable and assign it some value but it is not possible to declare and use signal assignment inside the function.

3. Conversion functions are used to _________
a) Resolve value of a signal with multiple drivers
b) Convert one data type into another
c) Convert one data object into another
d) Resolve value of a constant with multiple drivers
Answer: b
Clarification: Conversion functions are the functions which are used to convert any object of one data type into another data type. Some of such conversion functions are predefined in the packages. For example, CONV_INTEGER() converts the parameter into an integer value.

4. The variables declared inside a function retain their values between two function calls.
a) True
b) False
Answer: b
Clarification: A function may declare local variables which are accessible inside the function only. These variables don’t retain their values between successive calls but are reinitialized each time the function is called.

5. The minimum number of parameters that must be there in a function is ___________
a) 0
b) 1
c) 2
d) 3
Answer: a
Clarification: Yes, It is possible to have a function which has no parameter specified in the parameter list. If we don’t need to pass any information to the function from the main code, then there is no need to use any parameter in the list.

6. Which of the following is not the legal name of a function?
a) abc
b) +
c) then
d) my_func
Answer: c
Clarification: As for all other identifiers, the name may not be any reserved word of VHDL and can have alphanumeric characters and an underscore sign. The only different thing with functions is that the name of function can be any operator sign also.

7. In the following code, which of the lines corresponds to the function call and function definition?

L1 : ARCHITECTURE adder OF adder IS
L2 : BEGIN
L3 : x <= sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC);
L4 : END adder;
L5 : FUNCTION sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC) RETURN STD_LOGIC IS
L6 : VARIABLE c : INTEGER;
L7 : BEGIN
L8 : c<= a OR b;
L9 : RETURN c;
L10 : END sum;

a) L5, L3
b) L5, L9
c) L3, L7
d) L3, L5
Answer: d
Clarification: Function call is when a function is invoked as an expression and the definition of function is where the whole description of function is given. Therefore, L3 corresponds to a function call and L5 is where function definition starts.

8. What is the ease provided by using functions?
a) Easy debugging
b) Easy reading
c) Easy calling
d) Easy implementation
Answer: a
Clarification: Using function results in easy debugging. Since reading and maintaining code is easy while using functions. Usually, the architecture of a code is very big and therefore, causes difficulty in debugging. So, by using functions, debugging is easy.

9. If a function has an operator sign as its name, then what will be the purpose of that function?
a) Conversion
b) Overloading
c) Resolution
d) Define the data type
Answer: b
Clarification: When we want to make any operator behave differently, then we can define a function whose name will be same as the operator. This process of using an operator in a different manner is called the operator overloading.

10. What is the alternative for specifying the vector size in the function?
a) Not using arrays
b) Defining every single element differently
c) Defining a subtype
d) Using bit vector
Answer: c
Clarification: Sometimes, it is necessary to use arrays. In functions, it is not possible to define the size of array or vector we are using. Instead, we can define a subtype for the same which can be used easily as a parameter to the function.

VHDL for Campus Interviews, .