Category: VHDL Objective Questions

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Implementing Gates with Different Modelling – 1”.

1. Which of the following is a basic building block of digital logic?
a) Wires
b) Nets
c) Gates
d) Flip-flops
Answer: c
Clarification: Any kind of digital logic can be synthesized by basic logic gates like or gate, and gate, not gate, etc. By using these simple gates, we may synthesize many difficult circuits or functions. So, gates are the building block for any digital logic.

2. Which of the following gate is a universal gate?
a) AND
b) NAND
c) EXOR
d) EXNOR
Answer: b
Clarification: NAND and NOR are two universal gates. They are called so because we may implement any kind of basic logic gate by using any of these two universal logic gates. By using NAND or NOR, we may implement AND, OR, NOT and EXOR gates.

3. By how many modeling styles, the gates in VHDL can be implemented?
a) 1
b) 2
c) 3
d) 4
Answer: c
Clarification: There are three modeling styles in VHDL in which we may implement any kind of logic or logic gate. These modeling styles are behavioral modeling, dataflow modeling and structural modeling.

4. Which of the following is not needed when modeling a simple gate?
a) Library
b) Entity
c) Architecture
d) Configuration
Answer: d
Clarification: Modeling a gate is a really easy task. There is no need for adding some CONFIGURATIONS to the design. The gates can be designed with any modeling style without using any kind of configuration statement. Also, describing architecture is essential along with entity. Package is needed to have some basic functions.

5. Which kind of modeling is used in the following description?

ARCHITECTURE my_arch OF my_design IS
BEGIN
c<= a OR b;
END my_arch;

a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow
Answer: b
Clarification: In such cases, where the direct relation between inputs and outputs are described. A flow of data from the input side to the output side is described by using logic functions. Therefore, it is the case of dataflow modeling.

6. What is the type of modeling used in the code given below?

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
       ‘0’ WHEN OTHERS;
END my_arch;

a) Behavioral
b) Dataflow
c) Structural
d) Combinational
Answer: a
Clarification: When the architecture describes the behavior of the circuit with respect to different combinations of inputs, then it is called behavioral modeling. The behavioral modeling uses a selected assignment to show the value of output for different inputs.

7. The architecture describes _______ gate implemented by _________ modeling.

ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= NOT(a OR b);
END my_arch;

a) Or, behavioral
b) Not, Dataflow
c) Nor, behavioral
d) Nor, Dataflow
Answer: d
Clarification: Since the logic function is used to show the flow of data from input to the output. Therefore, The architecture describes the dataflow model of a gate. Also, the function is a not function performed on the output of or function. Therefore, the design is for NOR gate.

8. Which logic gate is described by the following model, also specify the type of modeling used?

ARCHITECTURE my_arch OF my_design IS
BEGIN
WITH ab SELECT
y <= 0 WHEN “11”
        1 WHEN OTHERS
END my_arch;

a) NAND, Behavioral
b) NOR, Behavioral
c) NAND, Dataflow
d) NOR, Dataflow
Answer: a
Clarification: It is clear from the architecture that the description represents a behavioral model. Now, the gate described must be the one which has low output when all of its inputs are low. Otherwise, the output is high. This is the case with NAND gate. So, the given logic is behavioral model of NAND gate.

9. Which of the logic gate is described by the following model?

ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT my_comp IS
PORT( a, b : IN std_logic;
             y     : OUT std_logic);
END COMPONENT;
L1 : my_comp PORTMAP( x, y, z);
END my_arch;

a) OR
b) NOT
c) AND
d) Can’t be determined
Answer: d
Clarification: The description is the structural model for any gate. But, it is not possible to determine which kind of gate it is. The given information is not sufficient to determine the type of the gain. It can be concluded that structural model alone is not adequate to describe any component completely.

10. The design below can’t be of ________ gate.

ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT or_comp IS
PORT( a, b : IN std_logic;
             y     : OUT std_logic);
END COMPONENT;
L1 : or_comp PORTMAP( x, y, z);
END my_arch;

a) AND
b) OR
c) NOT
d) NAND
Answer: c
Clarification: This is up to the user, what name he/she wants to give to the component. For example, a user can name an AND gate as or_gate. The name can’t describe what logic is going to be performed by the component. Here, all the gates except NOT have two inputs. Also, the component described has two ports. Therefore, the component can’t be a NOT gate.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on User defined Data Types”.

1. How the keyword “TYPE” is used?
a) TYPE datatype_name IS type_from_predefined_datatypes;
b) TYPE datatype_name IS datatype_range;
c) TYPE datatype_range IS datatype_name;
d) USE TYPE datatype_range IS datatype_name;
Answer: b
Clarification: The keyword TYPE is used to define new data type if any user wants to define for its own. The syntax for keyword is- TYPE datatype_name IS datatype_range. So, the new data type can have the values defined in range section of the declaration.

2. Which of the following is a wrong declaration for a new data type?
a) TYPE my_logic IS RANGE 0 to 100;
b) TYPE my_logic IS (‘0’, ‘1’, ‘2’);
c) TYPE my_logic IS ARRAY (0 TO 3) OF BIT;
d) TYPE my_logic IS <0 TO 20 >
Answer: d
Clarification: TYPE can be used in three forms as shown above. For defining range, there are two methods as illustrated in option TYPE my_logic IS RANGE 0 to 100; and option TYPE my_logic IS (‘0’, ‘1’, ‘2’);. If we want to define a user defined array then the sytanx like option TYPE my_logic IS ARRAY (0 TO 3) OF BIT; follows. But, we can’t define range by using <> sign.

3. One can’t define an array without any constraints in VHDL.
a) True
b) False
Answer: b
Clarification: We can define an array without any constraints in VHDL. When there are no constraints in array then it can have any number of elements. For example, TYPE my_type IS ARRAY (RANGE <>) OF BIT; this declaration defines an array of BIT data type without any constraint on the number of elements in the array.

4. A SUBTYPE can be defined as _________
a) A TYPE under a TYPE (nested)
b) A type of INTEGER datatype
c) A TYPE with some constraint
d) A TYPE without any constraint
Answer: c
Clarification: A SUBTYPE is a TYPE with some constraints. TYPE can be predefined data type and it can also be any user defined data type. But if SUBTYPE is derived from user defined datatype, then we first have to declare the type along with its range and then subtype can be defined.

5. Which of the following is the correct syntax for declaring a SUBTYPE?
a) TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
b) SUBTYPE subtype_name IS subtype_range TYPE type_name
c) SUBTYPE subtype_name TYPE type_name IS subtype_range
d) SUBTYPE subtype_name IS TYPE subtype_range
Answer: d
Clarification: The correct way to define a SUBTYPE is the syntax shown in option d. For example, if we want to define a SUBTYPE of STD_LOGIC with 3 values only like X, 0 and 1. We can define it as SUBTYPE my _ subtype IS STD_LOGIC RANGE ‘X’ TO ‘1’.

6. Which of the following can’t be the value of x? Refer to the VHDL code given below.

TYPE color IS (red, green, blue, black, white, gray);
SUBTYPE primary IS color RANGE red to blue;
VARIABLE x: primary;

a) White
b) Red
c) Green
d) Blue
Answer: a
Clarification: PRIMARY is a subtype of COLOR as declared in the code. The range of PRIMARY is declared “red” to “blue”. It means that an object of Primary type can have values red, green or blue. So White can’t be assigned to x.

7. Look at the following declarations:

TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); 
TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;

How many total bits can be stored in these arrays?
a) 16
b) 9
c) 64
d) 27
Answer: c
Clarification: First of all, array1 is array of BIT_VECTOR type that means it contains 4 BIT_VECTOR. One BIT_VECTOR is here declared to be consisting of 4 bits. Therefore, Array 1 can have 16 bits. Now, array2 is an array of 4 array1. Therefore, total bits are 4 × 16 = 64.

8. Refer to the four declarations below, which of the following is not a 2 dimensional array?

TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC;
TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 );
TYPE array3 IS ARRAY (2 DOWNTO 0 )  OF array2;
TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;

a) array4
b) array3
c) array2
d) array1
Answer: b
Clarification: Here, array1 is a 2-D array with 4 rows and 2 columns (3 DOWNTO 0 and 1 DOWNTO 0) of STD_LOGIC type. Though, array2 declaration looks like 1D array, but it is 2D array, since it is of type STD_LOGIC_VECTOR, which is already a 1D array, so array2 is a 2D array. Similarly array4 is 4 × 4 matrix. But, array3 is a 3D array. Because it is 1D array of 2D array named as array2.

9. User can define its own integer data type.
a) True
b) False
Answer: a
Clarification: In VHDL, user can define either its own integer type or enumerated type. User defined integer type must always be a subset of predefined datatype. User can define the integer with some desired range. For example, we can define any integer named as my_integer with range 0 to 32 as given: TYPE my_integer IS RANGE 0 TO 32; in this way, one can define a subset of integer.

10. Which of the following is a SUBTYPE of INTEGER?
a) NATURAL
b) REAL
c) CHARACTER
d) STD_LOGIC
Answer: a
Clarification: We can say that NATURAL is a subtype of INTEGER. The range of NATURAL datatype is 0 to 2³¹-1, whereas the range of INTEGER is – (2³¹-1) to (2³¹-1). Therefore, it can be written as SUBTYPE NATURAL IS INTEGER RANGE 0 TO 2147483647.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “IF Statement”.

1. What kind of statement is the IF statement?
a) Concurrent
b) Sequential
c) Assignment
d) Selected assignment
Answer: b
Clarification: IF statement is a sequential statement which appears inside a process, function or subprogram. This statement is used to execute some block of statements if a condition executed comes to be true.

2. Which of the following keyword is not associated with IF statement?
a) ELSE
b) THEN
c) ELSIF
d) WHEN
Answer: d
Clarification: The IF statement can use the keywords ELSIF, THEN and ELSE but not the keyword WHEN. IF statement is followed by a condition which is followed by the keyword THEN. After which to add more conditions one can use ELSIF and ELSE keywords.

3. Which of the following represents the correct order for keywords?
a) IF, THEN, ELSIF, THEN, ELSE
b) IF, ELSE, THEN, ELSIF, THEN
c) IF, ELSIF, THEN, ELSE, THEN
d) IF, THEN, ELSE, THEN, ELSIF
Answer: a
Clarification: In case of IF statement, the keyword IF is followed by the condition and then the keyword THEN. After this any other condition is entered by using ELSIF keyword and all the other exceptions are handled by using ELSE keyword. So, the correct order is shown in option a which is IF, THEN, ELSIF, THEN, ELSE.

4. What is the correct syntax for defining an IF statement?
a)

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE (condition) THEN
    statements;
    END IF;

b)

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE 
    statements;
    END IF;

c)

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE (condition)
    statements;
    END IF-ELSE;

d)

    IF (condition) THEN
    statements;
    ELSIF (condition) THEN
    statements;
    ….;
    ELSE 
    statements;
    END IF-ELSE;

View Answer

Answer: b
Clarification: For a sequential IF statement, the condition is evaluated and if it is found to be true then the statements under IF are executed and after that the sequence of ELSIFs is used and finally an ELSE is used and it is ended by using END keyword followed by IF.

5. If the condition of IF statement is an expression, then what should be the type of the result of the expression?
a) Bit
b) Std_logic
c) Boolean
d) Integer
Answer: c
Clarification: It doesn’t matter what is the type of the expression, the result must be of Boolean type. It can have only two values which may be either TRUE or FALSE. If the result is true, THEN the statements under IF are executed otherwise ELSE is executed.

6. In the following lines, what should be the value of signal y, if a and b both are at logic high?

PROCESS (a, b)
BEGIN
IF( a XOR b <=’1’)
y <= ‘1’;
ELSIF (a AND b <= ‘0’)
y &lt;= a;
ELSE
y &lt;= ‘0’;
END IF;
END PROCESS;

a) a
b) b
c) 0
d) 1
Answer: c
Clarification: At the time of synthesis, first the condition of IF statement is tested and it is found to be FALSE, so the statements under IF statements are skipped and the condition of ELSIF is tested. That condition again comes to be FALSE and hence the statement under else is executed. So, y is assigned 1.

7. It is possible to use nested IF in VHDL.
a) True
b) False
Answer: a
Clarification: Like other traditional languages, it is possible to use an IF statement inside another IF statement. In this case, when one IF statement is used inside another IF statement, this is called the nested IF statement. This allows to use more than one condition simultaneously.

8. Which of the following condition has topmost priority?
a) IF
b) ELSIF
c) ELSE
d) THEN
Answer: a
Clarification: IF has the topmost priority which means the remaining block will be executed only if the condition under IF gives FALSE. Otherwise, if it is true, then the block is shifted until END IF statement. After the IF condition, the next priority is ELSIF condition. ELSE is executed only if every preceding condition is FALSE.

9. What logic is described in the following logic?

PROCESS (a, b)
IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN
y <= ‘1’;
ELSIF (a = ‘1’ AND b= ‘1’) THEN
y <= ‘0’;
ELSE
 y <= ‘0’;
END IF

a) EXOR
b) EXNOR
c) AND
d) NOR
Answer: a
Clarification: Here, in the given code, the output is 1 if either a is 1 or b is 1. In the ELSIF, the condition is that the output will be zero if both the inputs are 1. So, both inputs can’t be high at the same time. Therefore, the logic described is exclusive OR logic.

10. One IF statement can have multiple ___________
a) IF
b) ELSIF
c) ELSE
d) CASE
Answer: b
Clarification: It is possible to have multiple ELSIF parts within one IF – END IF block. The IF statement can have multiple ELSIF parts but can have only one ELSE statement part. ELSE part will be executed after each of the ELSIF part is checked and found to be FALSE.

11. More than one sequential statement can exist between each statement part.
a) True
b) False
Answer: a
Clarification: Yes, It is not necessary that within a single IF or ELSIF, only one sequential statement is allowed. Multiple statements can be there between each statement part. Unlike, traditional languages it doesn’t need {} to write multiple statements.

12. If a user gets an error at the time of simulation which is “ the IF statement is illegal” what could be the reason?
a) Using IF statement in architecture body
b) Using IF statement without ELSE
c) Using multiple ELSE statements
d) Using concurrent assignment in the IF
Answer: a
Clarification: It is not allowed to use IF in the architecture body directly. IF statement is a sequential statement and hence can be used in a process, function or procedure. However, using IF statement without ELSE is not any error, doing this is possible. The only error is that it can’t be used in the concurrent.

13. In a clocked process, IF statement is used to __________
a) To run statements sequentially
b) To use concurrent assignment within process
c) To detect the clock signal
d) To implement sequential circuit
Answer: c
Clarification: A clocked process is the process which uses a clock signal to design the circuit. In such process one may need to detect the rising or falling edge of the clock. For this purpose, IF statement can be used to detect the occurrence of a clock.

14. What will be the output in the following code?

ARCHITECTURE my_logic OF my_design IS
BEGIN
a <= 1;
b <= 1;
PROCESS (a, b)
BEGIN
IF (a AND b = 1) THEN
output <= a;
ELSIF (a OR b = 1) THEN
output <= b;
ELSE
output <= 0;
END IF;
END PROCESS;
END my_logic;

a) 0
b) 1
c) b
d) a
Answer: d
Clarification: Since the condition under IF is true so the statements under IF will be executed and hence output will be assigned the value of signal a. Though the condition under ELSIF is also TRUE but IF has the highest priority so all the following ELSIFs will be ignored. This is the problem in IF statement.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Procedures – 1”.

1. Procedures are invoked as _________
a) Statements
b) Expressions
c) Values
d) Assignments
Answer: a
Clarification: Unlike functions, procedures are invoked as a statement. Functions are always invoked as expressions as a part of the assignment statement but procedures are directly called as statements only. No assignment operator is needed.

2. Procedures are useful when _________
a) Functions are not synthesizable
b) Signals are needed to be declare
c) Multiple values are needed as a result
d) Architecture can’t contain some statement
Answer: c
Clarification: Procedures usually returns many values, which is not possible with the case of function. So, procedures are useful when there are multiple results coming from the procedure. Note that procedure can return single value as well.

3. Which of the following is correct syntax for procedure body?
a)

    PROCEDURE procedure_name (parameter_list) IS
    BEGIN
    declarations;
    sequential_statements;
    END PROCEDURE;

b)

    PROCEDURE procedure_name (parameter_list) IS
    declarations;
    BEGIN
    sequential_statements;
    END procedure_name;

c)

    PROCEDURE procedure_name (parameter_list) IS
    declarations;
    BEGIN
    sequential_statements;
    concureent_statements;
    END PROCEDURE;

d)

    PROCEDURE procedure_name (parameter_list) IS
    declarations;
    BEGIN
    sequential_statements;
    concurrent_statements;
    END procedure_name;

View Answer

Answer: b
Clarification: The procedure definition is very similar to the function definition. It starts with the keyword PROCEDURE followed by the name of procedure and then the parameter list. Then local declarations are made within the procedure body, which are separated from the statements part by the keyword begin. Then the procedure body is ended by the keyword END followed by name of procedure.

4. Procedure doesn’t have a return type.
a) True
b) False
Answer: a
Clarification: Functions always have a return type which specifies the type of value which is returned by the function. But, procedures return multiple values; therefore, it is not possible to use a single return type. So, There is no return type for a procedure.

5. Which of the following could be the objects in the parameter list of a procedure?
a) CONSTANTS, VARIABLES
b) VARIABLES, SIGNALS
c) CONSTANTS, SIGNALS
d) CONSTANT, SIGNALS, VARIABLES
Answer: d
Clarification: A procedure may have any of three objects in its parameter list. A SIGNAL, CONSTANT as well as a VARIABLE can be used as a parameter to a procedure. In functions, only signals and constants can be parameters.

6. A procedure can’t contain a _______ statement.
a) WAIT
b) IF
c) RETURN
d) CASE
Answer: c
Clarification: A procedure, unlike functions, may contain WAIT statement but it doesn’t include any return statement. The assignments made in the procedure are considered as the values which are needed to be returned to the main code.

7. The parameter of a procedure can have any of the three modes.
a) True
b) False
Answer: a
Clarification: A procedure can have any number of IN, OUT or INOUT parameters which can be signals, constants or variables. There is no restriction on the mode of the signal It may be any of the three modes which are IN, OUT or INOUT.

8. Which of the following is the default class of any parameter with its mode as IN?
a) SIGNAL
b) CONSTANT
c) VARIABLE
d) SIGNAL or VARIABLE
Answer: b
Clarification: The default class for any IN mode parameter is CONSTANT. It means that if no mode is specified the parameters of mode IN are interpreted as class CONSTANT.

9. Which of the following is the default mode of a parameter of procedure?
a) IN
b) OUT
c) INOUT
d) IN or INOUT
Answer: a
Clarification: If no mode is specified in the front of a parameter, then it is considered as an input signal or of a mode IN. So, The default mode for a parameter of a procedure is IN mode which is similar to the functions.

10. It is given that the mode of a parameter is OUT mode but its class is not specified by the user. To which class does it belong?
a) INTEGER
b) CONSTANT
c) VARIABLE
d) SIGNAL
Answer: c
Clarification: The CONSTANT is the default class for the parameters of mode IN only. For other parameters that have their mode either as OUT or as INOUT the default class is considered as VARIABLE class.

This set of Basic VHDL Questions and Answers on “Implementing Gates with Different Modelling – 2”.

1. What is the minimum number of NAND gates required to implement an EXOR gate?
a) 2
b) 3
c) 4
d) 5
Answer: c
Clarification: We can implement an EXOR gate with a minimum of 4 NAND gates. However, when we follow the conventional way to convert an EXOR logic into the NADN logic, then the number of logic gates required is 5, but 1 of them is redundant and therefore, we can implement EXOR get by using 4 NAND gates.

2. Which of the following logic describes the EXOR gate?
a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));
b) y <= ((not a) OR b) AND (a OR (not b))
c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
d) y <= ((not a) AND b) OR (a AND (not b));
Answer: d
Clarification: EXOR function or Exclusive OR is a function in which two inputs of the gate can’t be at high level exclusively, in that case the output will be low. It is described by Y = A’B + AB’. This function is described in the VHDL terms by using option d. Therefore, option d represents EXOR gate.

3. What logic circuit is described by the following code?

ARCHITECTURE gate OF my_gate IS
BEGIN
WITH ab SELECT
y<= 0 WHEN “01” OR “10”;
        1 WHEN OTHERS;
END gate;

a) NAND
b) NOR
c) EXOR
d) EXNOR
Answer: d
Clarification: Since the output is high when all the two inputs are either high or low. Otherwise, the output is low. This is the case opposite of EXOR gate. So, this must be EXNOR gate.

4. Sometimes gates modeled with ________ modeling may behave differently.
a) Dataflow
b) Behavioral
c) Structural
d) Structural and Behavioral
Answer: a
Clarification: Sometimes, dataflow modeling doesn’t behave as we want it to. This different behavior can be with any of the gate. For example, OR gate may behave as AND gate for instance. This occurs at the time of synthesis due to switches in the switch bank.

5. The odd behavior of gates in dataflow modeling may be the result of ________
a) Sequential statements
b) Wrong logic definitions
c) Concurrency
d) Inappropriate assignments
Answer: c
Clarification: The VHDL code is concurrent code and it has its own advantages and disadvantages. Concurrency of VHDL results in faster execution. In some PAL or PLA device, it may be like executing AND after OR execution which may result in different results.

6. Which of the following option represents a structural model for not gate?
a)

    Architecture not_gate OF my_func IS
    BEGIN
    x: IN STD_LOGIC;
    y: OUT STD_LOGIC;
    END not_gate;

b)

    Architecture not_gate OF my_func IS
    BEGIN
    x: IN STD_LOGIC;
    y: OUT STD_LOGIC;
    y<= NOT x;
    END not_gate;

c)

   Architecture not_gate OF my_func IS
    BEGIN
   COMPONENT NOT IS
   Port(  x: IN STD_LOGIC;
   y: OUT STD_LOGIC);
   END COMPONENT;
    END not_gate;

d)

   Architecture not_gate OF my_func IS
    BEGIN
    COMPONENT not1 IS
    PORT( x: IN STD_LOGIC;
    y: OUT STD_LOGIC);
    END COMPONENT;
    END not_gate;

View Answer

Answer: d
Clarification: Since the structural modeling defines only the components with their input and output ports. But the name of component can’t be same as any reserved word of VHDL.

7. In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
a) Incorrect interconnections
b) Concurrent execution of statements
c) Mismatch of ports name and switches
d) Wrong libraries included
Answer: b
Clarification: A CPLD is a device which has many input outputs and logic gates and it also includes interconnection between them. The inputs are arranged in the form of switch banks, the gate may perform different due to concurrency of the statement. Due to concurrent statements, the state of a switch can vary and which can affect the output.

8. For gates, which of the following modeling style will corresponds to shortest code?
a) Behavioral
b) Data flow
c) Structural
d) Both data flow and behavioral
Answer: b
Clarification: Since in case of dataflow modeling we just need to define the relation between inputs and outputs using some logical function. So, gates can be modeled be using dataflow style in just one line. Whereas Behavioral needs selected assignment and structural used component declaration and instantiation.

9. Generally, structural modeling is used with another modeling style.
a) True
b) False
Answer: a
Clarification: We can’t describe a logic gate or circuit by using a structural model alone. At least one more architecture is needed to properly describe the behavior of the circuit. So generally more than one architectures are used.

10. Which of the following doesn’t corresponds to NAND gate?
a)

b)

c)

d)

   WITH ab SELECT
    y <= 0 WHEN ”11”
    1 WHEN OTHERS

View Answer

Answer: c
Clarification: Option a corresponds to NAND gate and option d is also the truth table of NAND gate. Now in option b, the gate described is bubbled OR gate which is equivalent to NAND gate. Option c corresponds to bubbled AND which is equivalent to NOR gate.

basic questions and answers on all areas of VHDL, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Data Conversion”.

1. Refer to the VHDL code given below, which of the following line has error?

Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’;
Line 2: SIGNAL a: BIT;
Line 3: SIGNAL b: STD_LOGIC;
Line 4: SIGNAL c: my_logic;
Line 5: b<=a;
Line 6: b<=c;

a) Line 1
b) Line 4
c) Line 5
d) Line 6
Answer: c
Clarification: As a is a SIGNAL of BIT type and b is a SIGNAL of std_logic type; so we can’t perform direct operations on these data. For assigning the value of one data type to another data type, we need to use some type of data conversion. Without data conversion, it is illegal. However, line 6 is legal, because STD_LOGIC and my_logic both has same “base”, which means that my_logic is a subset of STD_LOGIC.

2. One can perform basic operations between different data types.
a) True
b) False
Answer: b
Clarification: VHDL is a strongly typed language i.e. it has very strict rules about predefined and user defined data types. So, we can’t perform any operation between data of different types. Although, it is possible to perform operation between two data types with same base.

3. How to correctly assign the value of 2x+10 to y in the following VHDL code?

TYPE long IS INTEGER RANGE -1000 TO 1000;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;

a) y <= 2*x + 10;
b) long y <= long 2*x + 10;
c) short y <= long (2*x + 10);
d) y <= long (2*x + 10);
Answer: d
Clarification: For all the data types with same base, the conversion can be carried out at the time of operation itself. Therefore, if we want to assign a value of ‘short’ type to a variable of ‘long’ type; we may simply write ‘long’ just after the assignment operator. By doing so, user can convert one type into another. Note that, it is only possible if and only if both the types are having same base.

4. In the VHDL code given below, what will be the error at the time of compilation?

TYPE my_int IS INTEGER RANGE -32 TO 32;
TYPE other_int IS INTEGER RANGE 0 TO 100;
SIGNAL x : my_int;
SIGNAL y : other_int;
y <= x + 2;
…

a) Type mismatch
b) Syntax problem
c) No declaration
d) Can’t compile
Answer: a
Clarification: Here, we have two user defined data types which are my_int and other_int with the same base. But, we can’t directly perform any operation between the signals of these two different types. Such kind of error is called “Type Mismatch” error. First, user needs to convert my_int to other_int. so, the correct assignment statement will be:- y<= other_int (x + 2);

5. Which of the following package of IEEE contains most of the data conversion functions?
a) std_logic_1164
b) std
c) std_logic_arith
d) std_logic
Answer: c
Clarification: Most of the conversion functions are defined in the std_logic_arith package of IEEE library. When user need to convert one type of data into another type and both have different bases, then it is essential that he/she need to declare the std_logic_arith package in the library declaration part. However, when we need to convert the data types with same base, then the functions are defined in std_logic_1164 package.

6. If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?
a) STD_LOGIC VECTOR
b) STD_ULOGIC
c) INTEGER
d) SIGNED
Answer: a
Clarification: The function conv_integer(p) is used to convert the parameter ‘p’ of any type excluding STD_LOGIC_VECTOR into the integer type. This function can covert INTEGER, SIGNED, UNSIGNED, STD_ULOGIC types into integer type. After converting only, we can use ‘p’ as INTEGER type.

7. In the function conv_unsigned(p, b), what does p and b refers to?
a) p is the data object to be converted and b is the base of that data object
b) p is the data object to be converted amd b is the bits needed in converted variable
c) p is the parameter to be converted and b is the bits of same parameter
d) p is the type of data to be converted and b is the type of data into which p should be converted
Answer: b
Clarification: The function conv_unsigned is used to convert different data types in UNSIGNED type. Two arguments are used in this function which are p and b. p is the data object which we need to convert and b represents the no of bits in UNSIGNED type. So, conv_unsigned(p,b) converts the parameter ‘p’ of INTEGER, SIGNED, UNSIGNED, STD_ULGOIC into UNSIGNED type of size ‘b’ bits.

8. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?
a) conv_integer_signed(p,b);
b) conv_signed_integer(p,b);
c) conv_signed(p,b);
d) conv_signed_p(b);
Answer: c
Clarification: To convert INTEGER, SIGNED, UNSIGNED and STD_ULOGIC types into SIGNED type, the function conv_signed is used. The correct way to use this function is :- conv_signed(p,b) where p is the object to be converted and b is the number of bits in SIGNED type.

9. The function conv_std_logic_vector(p,b) is used for_______
a) Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type
b) Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits
c) Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits
d) Converting STD_LOGIC into STD_LOGIC_VECTOR
Answer: b
Clarification: This function is used to convert the parameter ‘p’ of type INTEGER, UNSIGNED, SIGNED or STD_LOGIC into STD_LOGIC_VECTOR. Note that the size of converted variable will be ‘b’ bits. So, b represents the number of bits in the converted object.

10. What will be the value of y after the execution of the following VHDL code?

Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
…
SIGNAL m : UNSIGNED (3 DOWNTO 0);
SIGNAL n : UNSIGNED (3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0);
y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);
…

a) 8- bit STD_LOGIC_VECTOR m+n
b) 8- bit UNSIGNED m+n
c) 4- bit STD_LOGIC m+n
d) Error
Answer: a
Clarification: Here, the conversion function is used to convert the data objects into STD_LOGIC_VECTOR type. The operation ‘m+n’ is completely legal since both are UNSIGNED type, after this operation the result is converted into STD_LOGIC_VECTOR with size ‘8’ bits. So, the values assigned to ‘y’ will be of STD_LOGIC_VECTOR type of 8 bits.

11. Refer to the VHDL code given below, what will be the output?

Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
…
SIGNAL a : IN INTEGER;
SIGNAL b : IN UNSIGNED (3 DOWNTO 0);
SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
y <<=CONV_STD_LOGIC_VECTOR ((a+b), 8);
…

a) 8- bit STD_LOGIC_VECTOR a+b
b) 8- bit UNSIGNED a+b
c) 4- bit STD_LOGIC_VECTOR a+b
d) Error
Answer: d
Clarification: The code is not completely legal. There will be an error of type mismatch. Since a and b are two completely different data types, one is INTEGER and another is UNSIGNED. So, we can’t perform the operation ‘a+b’. Therefore, to perform this operation, first a and b need to be of same type, which can be done by converting INTEGER into UNSIGNED or vice-versa.