Category: VHDL Objective Questions

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Signal Kind Attributes”.

1. What is the basic use of signal kind attributes?
a) To check any event on signals
b) To check if a function is called
c) To check if a signal is IN or OUT mode
d) To check a clock signal
Answer: a
Clarification: Signal kind attributes can provide information about any signals. These attributes can be used to report whether a signal has changed its value, what was the last value and after what time the signal changed, etc.

2. Which of the following returns the Boolean type always?
a) ‘LAST_VALUE
b) ‘LAST_EVENT
c) ‘EVENT
d) ‘STABLE
Answer: c
Clarification: ‘EVENT is an attribute which returns a Boolean value always. It returns true if any transition has taken place on the given signal during the current delta. Otherwise, it returns false. It always takes a signal as its object and detects any change on the value.

3. Signal kind attributes can’t have variables as their objects.
a) True
b) False
Answer: a
Clarification: Signal kind attributes are called so because they provide information about any signal. Unlike value kind and function kind in which variables can be used objects with attributes, it is not possible to use any data object with signal kind attributes except signals.

4. Refer to the statement given below, it is used for detecting _________

IF (clk’EVENT and clk = ‘0’)

a) Rising edge of the clock signal
b) Falling edge of the clock signal
c) Clock signal frequency
d) Time period of clock signal
Answer: b
Clarification: As described earlier, ‘EVENT will detect any change on the clock signal. This attribute is here used in conjunction with a condition that clock signal should be zero. So, the statement is used to detect the trailing or falling edge of the clock signal.

5. s’ACTIVE will return true if _________
a) Any transition from 0 to 1 on signal s during the current delta
b) Any transition from 1 to 0 on signal s during the current delta
c) Any change has occurred on the signal s during last 2 delta’s
d) Any change has occurred on the signal s during the current delta
Answer: d
Clarification: s’ACTIVE is an attribute which always returns the Boolean value always. It returns true if the signal is active during the current delta. It means the value will be true if any change has occurred on the signal during the current delta. Otherwise, it returns false.

6. Attribute s‘LAST_EVENT has a return value of ______ type.
a) BOOLEAN
b) TIME
c) INTEGER
d) Same as signal s type
Answer: b
Clarification: s’LAST_EVENT is an attribute which returns the time elapsed since the previous event occurred on the signals. This attribute is very useful for implementing timing checks like pulse width check, hold check etc.

7. What is the type of value returned by the s’DELAYED(time) attribute?
a) TIME
b) BOOLEAN
c) INTEGER
d) Same as signal s
Answer: d
Clarification: s’DELAYED attribute is used to create a delayed version of same signal, delayed by an amount specified in the argument. It creates the signal delayed by ‘time’ value. So, the return type will be same as that of signals.

8. Which of the following statement is correct to check the violation of hold time?
a) IF(clk’DELAYED(hold_time)’EVENT) THEN
b) IF(clk’DELAYED(hold_time) = ‘1’) THEN
c) IF(clk’DELAYED(hold_time) = ‘0’) THEN
d) IF(clk’DELAYED(hold_time) = ‘1’ AND clk’DELAYED(hold_time)’EVENT) THEN
Answer: d
Clarification: The signal is created by ‘DELAYED attribute which is delayed by hold time and then it must be used in conjunction with the ‘EVENT attribute to check any event on the signal generated. By doing this, one may check the hold time.

9. The attribute s’TRANSACTION creates a signal of type ______
a) BOOLEAN
b) BIT
c) INTEGER
d) Same as signal s
Answer: b
Clarification: s’TRANSACTION creates a signal of time BIT that toggles its value for every transaction of the signal it is attachted to. Whenever there is some change in signal s, the value of BIT signal is toogled either from 1 to 0 or from 0 to 1.

10. What is the use of s’TRANSACTION attribute?
a) Check the continuity
b) Check the hold time
c) Interrupt handling by using WAIT
d) Create a square wave
Answer: c
Clarification: The ‘TRANSACTION attribute is generally used with the WAIT statement to handle the interrupts. Without ‘TRANSACTION attribute, the WAIT statement is sensitive to the events only, but with ‘TRANSACTION it can be activated on every transaction on the BIT signal output of attribute.

.

This set of Tricky VHDL Questions and Answers on “Implementing Logic Functions with VHDL – 2”.

1. What do you use to perform basic logic functions in VHDL while creating concurrent code?
a) Operators
b) If statement
c) PROCESS
d) GENERATE
Answer: a
Clarification: Operators are the most basic ways of creating concurrent code. These operators may be logical, arithmetic, shift operators or so on. Generally, logical operators are used in logic functions.

2. In the implementation of following function by using NAND keyword only, can be done in _____ operations.

a) 2
b) 3
c) 4
d) 5
Answer: c
Clarification: The given logic function resembles the export operation. An EXOR gate can be implemented by using 4 NAND operations. Therefore, the NAND keyword will be used 4 times in implementation of this function.

3. The maximum number of parameters in port map() function while implementing logic function using gates only, is equal to ____________
a) Number of inputs
b) Number of outputs
c) Number of inputs + number of outputs
d) Infinite
Answer: c
Clarification: A port map function is used in structural modeling in which we use port map fumction to map a given structure. The parameters of port map identify the inputs and outputs of the circuit respectively starting from the left. Therefore, a port map can have maximum parameters as the sum of number of inputs and outputs of the port.

4. Which of the following is not representing a nibble?
a) x<= “0101”
b) x<= STD_LOGIC_VECTOR (0 TO 4)
c) x<= STD_LOGIC_VECTOR(3 DOWNTO 0)
d) x<= BIT_VECTOR (1 TO 4)
Answer: b
Clarification: A nibble is a group of 4 bits. In case of option x<= “0101”, it is clear that x is a group of 4 bits. Similarly in x<= STD_LOGIC_VECTOR(3 DOWNTO 0) and x<= BIT_VECTOR (1 TO 4), we have four bits. But, in option x<= STD_LOGIC_VECTOR (0 TO 4), we have 5 bits from 0 to 4. Therefore, option x<= STD_LOGIC_VECTOR (0 TO 4) is not a nibble.

5. In designing logic functions in VHDL, we can use arithmetic operators.
a) True
b) False
Answer: a
Clarification: It is completely legal to use arithmetic operator in implementation of a logic or Boolean function. We can obviously use arithmetic operators like +, -, * etc. in the logic functions, if required. It will not contain any error.

6. A “Multiplication by 2” logic is to be designed by using the VHDL code, which of the following operator can be used to implement the same?
a) SRL
b) SRA
c) SLA
d) SLL
Answer: d
Clarification: In binary number system, when we multiply a number by 2, it shifts one position to the left. For example, 4(0100), when multiplied by 2, it becomes 8(1000). So, it is clear that one can easily make multiplication by 2 logic by using a single operator called SLL or Shift Left Logical.

7. What kind of logic is represented by the given code?

ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= x SRL 2;
END my_func;

a) Divide by 2
b) Divide by 4
c) Multiply by 2
d) Multiply by 4
Answer: b
Clarification: Since the code is using a shift right operator, therefore, it must be something to be divided. So, x is divided here and the result is stored in y. Here, the x is shifted to 2 positions right, which means that it is a divide by 4 (= 2²) logic.

8. What information is not provided by the given logic’s output?

ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= x SRL 2;
END my_func;

a) Result of the operation
b) Operands used
c) Remainder of the operation
d) Everything about the operation will be determined
Answer: c
Clarification: Because only a shift operator is used this will act as divide by 4 logic. But, if there is any remainder of the operation, that can’t be determined by the output. For that purpose a statement with REM operator must be used.

9. A user wants to implement a logic by using VHDL. In which he has inputs from two sensors which are smoke sensor and water level detector. If any input is high, he has to turn on the respective alarm. Which of the following is representing the correct code for the given logic?
a)

ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;

b)

 ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘0’;
ELSE water_alarm = ‘1’;
END IF;
END PROCESS;
END alarm_control;

c)

ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘0’;
ELSE fire_alarm = ‘1’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;

d)

ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘0’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘0’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;

View Answer

Answer: a
Clarification: When the input to the controller is high from any of the sensor, then the respective alarm status should be high. This can be easily implemented by using IF control statements. So, by using IF statement, one can set the fire alarm if smoke sensor is giving a high input. Otherwise, water level detector will turn the water alarm on.

10. Optimized implementation of Boolean functions reduces the cost of implementation.
a) True
b) False
Answer: a
Clarification: By using a suitable method for optimization, the number of prime implicants will be reduced and hence less number of logical operations need to be performed in the VHDL code. This reduction will reduce the cost of implementation.

Tricky questions and answers on all areas of VHDL, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Generics”.

1. In which part of the VHDL code, generics are declared?
a) Package declaration
b) Entity
c) Architecture
d) Configurations
Answer: b
Clarification: Generics are a general mechanisms used to pass information to an instance of any entity and are declared in the entity itself. These are of constant type and are declared before port declarations. The declaration of generics is followed by the keyword GENERIC.

2. Which of the following is correct declaration for a generic?
a) GENERIC (name : type := initial_value);
b) GENERIC (type : name := initial_value);
c) GENERIC (name : type <= initial_value);
d) GENERIC ( ype : name <= initial_value);
Answer: a
Clarification: The declaration of generic is done in entity declaration part and the correct syntax to declare it is GENERIC ( parameter_name : parameter_type := initial_value). Since, generic is constant object, so := operator is used to assign the initial value.

3. What is the main use of the generic parameter?
a) Defining constant type
b) Assigning some initial value to constant
c) Reusability
d) Using constant type within the entity
Answer: c
Clarification: The purpose of defining a generic statement within an entity is to confer more flexibility and reusability. A generic parameter is basically used globally with some value. Whenever one want to reuse same thing again and again then defining it as a generic parameter will be useful rather than defining it again and again.

4. More than one generic parameter can be defined in a single entity.
a) True
b) False
Answer: a
Clarification: It is possible to define more than one parameter in an entity. If we want to define more than one generic parameter, then the two parameters must be separated by a semicolon. For example, GENERIC (n : INTEGER := 8; m : BIT_VECTOR := “0011”); In this declaration n and m are two different generics in which one is of INTEGER and another is BIT_VECTOR type.

5. Which of the following is true about Generics?
a) Generics can be assigned information as part of simulation run
b) Generics cannot be assigned information as part of simulation run
c) Generic passes data to an entity which is not instance specific
d) Results of simulation can modify the value of generics
Answer: b
Clarification: All the data passed to an entity is instance specific and this data can’t be assigned any information as a part of simulation run. The value of generic is not a simulation specific value but, it is a instance specific value which can’t be modified by the simulation results.

6. A generic can’t be declared in a component declaration.
a) True
b) False
Answer: b
Clarification: A generic can be declared in entity as well as in any component declaration statement. It is not necessary to define generic in entity only. If structural modeling is used, then generic can be used in component declaration statement too. However, it must be noted that the generic is declared before ports declaration.

7. In most synthesis tools, only generics of type ________ are supported.
a) INTEGER
b) REAL
c) BIT_VECTOR
d) STD_LOGIC
Answer: a
Clarification: Integer type is the only generics type which is synthesizable in most of the EDA tools. Whereas, in some cases all the types are synthesizable. It is possible to define any type of generic but the thing is that they may not be synthesized.

8. GENERIC (n : INTEGER := 8); In this statement, the mode of generic ‘n’ is _______
a) Integer
b) Real
c) Generic
d) No Mode
Answer: d
Clarification: Generics are a means of passing specific information into an entity. Generics can have only a type but no mode. Integer is the type of generic. Mode of any variable or signal defines its direction which means whether it is used as an input signal or output signal. Therefore, mode is not defined in the case of generics.

9. Which function is used to map a generic on design?
a) Port map()
b) Generic()
c) Generic map()
d) Port
Answer: c
Clarification: As generic is declared before a port in component and entity declaration. Similarly, to map a generic type, one can use generic map() function before port map() function in component instantiation part of the code. This function is used in structural modeling.

10. Generics in VHDL can be treated as _______
a) Global variable
b) Local variable
c) Variable
d) Signal
Answer: a
Clarification: Generics in VHDL can be taken as global variable which is declared once and is used in complete design. Unlike signals, generics doesn’t have a mode or direction and unlike variable the value of generics can’t be changed.

11. Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?
a) Number of outputs
b) Number of inputs
c) Intermediate signals
d) No parameter
Answer: b
Clarification: Generics are used where a single change of value can change it everywhere in the code. For example, if one wants to change the input sizes then it can be changed in entity and respective change is seen everywhere in the code. Since the number of outputs is constant and therefore no need to use number of outputs as generics.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “WAIT Statements – 1”.

1. WAIT statement can’t appear under _______ directly.
a) Architecture
b) Process
c) Procedure
d) Subprogram
Answer: a
Clarification: WAIT statement is a sequential statement which is similar to IF statement and its more than one form are available. Since it is a sequential statement, it can appear inside a process, procedure or subprogram, but can’t appear under architecture. In architecture only concurrent statements can be used.

2. Which of the following can’t be used in a process when it has any WAIT statement?
a) IF
b) CASE
c) LOOP
d) Sensitivity list
Answer: d
Clarification: One can’t use a WAIT statement along with sensitivity list. It can either have a sensitivity list or some WAIT statements. However, IF, CASE and LOOP are some other sequential statements which can be used when the process has sensitivity list. WAIT statement also contain signals to which the process is sensitive.

3. How many forms of WAIT statement are there in VHDL?
a) 1
b) 2
c) 3
d) 4
Answer: c
Clarification: There are three forms of WAIT statements among which all of them can be used for synchronous as well as asynchronous sequential code. Some sort of condition or time period is used to stop the execution of process and wait for some event to occur.

4. Which of the following is not the correct WAIT statement?
a) WAIT ON
b) WAIT WHILE
c) WAIT FOR
d) WAIT UNTIL
Answer: b
Clarification: WAIT ON, WAIT FOR and WAIT UNTIL are the three types of WAIT signals. There is no WAIT WHILE statement. WAIT ON, FOR and UNTIL are the different types which follow different syntax and different types of WAIT statement which suspends the process for some time.

5. WAIT UNTIL statements cause the process to wait ________
a) When a signal changes value
b) Until a condition is true
c) For a specific time period
d) When either a signal changes its value or a condition comes true
Answer: b
Clarification: WAIT UNTIL statement is a form of WAIT statement which causes the process to wait until a condition is true. It is mandatory that the type of condition used must be Boolean. It can be any kind of expression but the result must be of Boolean type.

6. What is the correct syntax for using a WAIT UNTIL statement?
a) WAIT UNTIL boolean_condition_or_expression;
b) WAIT UNTIL signal_name;
c) WAIT UNTIL time_value_or_expression;
d) WAIT UNTIL boolean_expression time_value;
Answer: a
Clarification: To write a WAIT UNTIL statement, a Boolean expression is used which causes the process to wait until the expression is true. Unlike IF, CASE and LOOP, the WAIT statement uses a semicolon at the end of the line.

7. What is the use of WAIT FOR statement?
a) To stop execution when the condition is false
b) To stop execution until a signal changes its value
c) To stop execution for a specific time period
d) To stop execution until the clock event occurs
Answer: c
Clarification: WAIT FOR statement is useful in the case when we want to suspend the process for a known time period. For example, a delay of 10 ns is used in case of a buffer execution then we can use a WAIT FOR statement.

8. How to define a WAIT FOR statement?
a) WAIT FOR signal_name;
b) WAIT FOR booelan_expression;
c) WAIT FOR clock_event;
d) WAIT FOR time_value;
Answer: d
Clarification: WAIT FOR statement can be used by writing the keyword WAIT FOR followed by a time expression. This time expression can be a simple value of time followed by units of time. Since the time is a physical literal of VHDL and its base unit is nanosecond (ns). So, ns is mostly used. For example, WAIT FOR 100 ns; is the correct syntax for WAIT FOR statement.

9. Which of the following is the correct use of WAIT ON statement?
a) To stop execution until a signal changes its value
b) To stop execution when a signal changes its value
c) To stop execution when a condition specified is true
d) To stop execution when a condition specified is false
Answer: a
Clarification: The WAIT ON statement puts the process on a hold until any of the signal listed changes its value. This statement is thus useful in detecting the clock events and other similar events. For example, WAIT ON clk will cause the process to wait until a clock event takes place.

10. Which of the following is correct syntax for WAIT ON statement?
a) WAIT ON signal_assignments;
b) WAIT ON boolean_condition;
c) WAIT ON signal_list;
d) WAIT ON time_expression;
Answer: c
Clarification: The keyword WAIT is followed by a signal list which is similar to the sensitivity list of the process and the list is used to detect the events. Whenever any signal on the list changes the process resumes the execution.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Type Kind and Range Kind Attributes”.

1. Which of the following is only a predefined type kind attribute?
a) ‘TYPE
b) ‘BASE
c) ‘RANGE
d) ‘RIGHT
Answer: b
Clarification: Type attributes return values of a kind type. There is only one type attribute which is T’BASE where T is any object. T’BASE will return the base type of object T. This object can be single, variable or constant.

2. T’BASE attribute can be used with another attribute only.
a) True
b) False
Answer: a
Clarification: T’BASE attribute returns the base type of a type or subtype. It can be used as the prefix to another attribute. It is available for all types and can’t be used independently. It must have a value kind or function kind attribute attached to it.

3. What will x’BASE and y’BASE return in the code given below?

TYPE color IS (red, blue, green, yellow, brown)
SUBTYPE color_gun IS color RANGE red TO green
VARIABLE x : color;
VARIABLE y : color_gun;

a) color, color_gun
b) color_gun, color
c) color, color
d) red, color
Answer: c
Clarification: As specified before, ‘BASE attribute will return the base type of any type or subtype. Here x is of the type color so x’BASE will return color. Similarly, y’BASE is of type color_gun which is a subtype with its base type color. So, y’BASE will also return color.

4. What will be the value of a in the statements given below?

TYPE color IS (red, green, blue, yellow, brown, black);
VARIABLE a : color;
a := color’BASE’RIGHT;
…

a) red
b) color
c) green
d) black
Answer: d
Clarification: Since ‘BASE attribute can’t be used independently, here it is used in conjunction with ‘RIGHT attribute. So, first of all color’BASE will return type color and then the ‘RIGHT attribute will return the rightmost value in the specified type. So, a will be assigned with black.

5. How many predefined attributes are there which are range kind attributes?
a) 1
b) 2
c) 3
d) 4
Answer: b
Clarification: There are two predefined attributes in VHDL which return a value kind of range. These two attributes are called Range kind attributes. The predefined range kind attributes are a’RANGE and a’REVERSE_RANGE.

6. The object of a range kind attribute can be __________
a) Any signal, variable or constant
b) An array
c) A constrained array
d) An unconstrained array
Answer: c
Clarification: Range kind attributes works only on constrained array types. The arrays which have defined bounds are called constrained array types. These attributes return the range of the given array.

7. Which of the following is the most appropriate use of range kind attributes?
a) In implementing CASE
b) In implementing LOOP
c) In implementing IF
d) In implementing ASSERT
Answer: b
Clarification: Since range kind attributes return a range of an array. This range can be used in defining the LOOP structure. For loop needs a counter which needs a range like 1 TO n. This range can be provided by the range kind attribute.

8. What will be the value of array16’RANGE and array16’REVERSE_RANGE, if the array16 is an object defined as below?

TYPE array16 IS ARRAY(15 DOWNTO 0) OF BIT

a) 15 DOWNTO 0, 0 TO 15
b) 0 TO 15, 15 DOWNTO 0
c) 0 TO 15, 0 TO 15
d) 15 DOWNTO 0, 15 DOWNTO 0
Answer: a
Clarification: ‘RANGE attribute will just give the range of array to which it is attached to. In this case, the range of array16 is 15 DOWNTO 0. The reverse range will just give the range in reverse order, which will be 0 TO 15.

9. Which of the following is a new predefined attribute in VHDL 93?
a) T’BASE
b) T’RANGE
c) T’EVENT
d) T’ASCENDING
Answer: d
Clarification: T’ASCEDING is defined in the VHDL-93 which returns a value of BOOLEAN type. It returns true if a constrained array has range defined in ascending order. Otherwise, if the range is defined like 15 DOWNTO 0 then it will return false.

10. Which of the following attribute is not synthesizable?
a) ‘RANGE
b) ‘EVENT
c) ‘BASE
d) ‘REVERSE_RANGE
Answer: c
Clarification: Since ‘BASE requires another attribute to use it. It is not supported by the logic synthesis tools. Only predefined attributes which are synthesizable are ‘RANGE, ‘REVERSE_RANGE, ‘LENGTH, ‘EVENT, ‘LEFT, ‘RIGHT, ‘HIGH, ‘LOW, LAST_VALUE and ‘STABLE.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Implementing Combinational Circuits with VHDL – 1”.

1. Which of the following is a not a characteristics of combinational circuits?
a) The output of combinational circuit depends on present input
b) There is no use of clock signal in combinational circuits
c) The output of combinational circuit depends on previous output
d) There is no storage element in combinational circuit
Answer: c
Clarification: A combinational circuit is the one which has no storage of previous output. The next state or output of the combinational circuit depends only on its present input and hence no clock signal is required.

2. Sequential code can’t be used to design combinational circuit.
a) True
b) False
Answer: b
Clarification: There is no restriction on usage of any kind of statements while realizing a combinational circuit. Combinational circuit may be implemented by using statements like IF, CASE etc.

3. Which of the following is not a combinational circuit?
a) Adder
b) Code convertor
c) Multiplexer
d) Counter
Answer: d
Clarification: Since counter makes use of either clock signal or previous output to determine next state. Therefore, counter is a sequential circuit and all the others like multiplexer, adder and code convertors are the examples of combinational circuit.

4. The code given below is a VHDL implementation of _________

ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
         x1 WHEN “01”;
         x2 WHEN “10”;
         x3 WHEN “11”;
END my_circuit;

a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX
Answer: a
Clarification: In the given architecture, the output is single (y), which is selected with the help of a and b. So, a and b are select lines and y is the output which is selected from 4 inputs. Therefore, it is the multiplexer circuit with 4 inputs and 1 output.

5. Which of the following line of the code contains an error?

L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4:   <= x1 WHEN x = ‘1’;
L5: END mux1;

a) L2
b) L3
c) L4
d) No error
Answer: d
Clarification: There is no error in the given piece of the code. However, there was no need to use WHEN in the line L4 because there is no other case to be selected from many inputs. Last case can be directly expressed without any use of WHEN.

6. In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?
a) WITH-SELECT
b) WITH-SELECT-WHEN
c) IF-ELSE
d) CASE
Answer: b
Clarification: Because only concurrent statements can be used, therefore, WITH-SELECT is the correct alternative for the method used by the user. But, WITH-SELECT also requires WHEN keyword to implement the selected assignment.

7. Which of the following entity declares the ports of a 3 by 8 decoder?
a)

    ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
     END decoder;

b)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
     END decoder;

c)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
     END decoder;

d)

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
     END decoder;

View Answer

Answer: d
Clarification: In a 3 by 8 decoder, there must be 3 inputs and 8 outputs. For 3 inputs the dimension of vector must be 2 DOWNTO 0 and for output the dimensions should be 7 DOWNTO 0. Therefore, option d is the correct port entity of the 3 by 8 decoder.

8. For using a process to implement a combinational circuit, which signals should be in the sensitivity list?
a) Inputs of the circuit
b) Outputs of the circuit
c) Both of the Inputs and Outputs
d) No signal should be in the sensitivity list
Answer: a
Clarification: In a process used for the implementation of the combinational circuit, all the input signals used which are to be read, should appear in its sensitivity list. In a combinational circuit, there can be many inputs and those inputs should appear in the sensitivity list of the process.

9. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
a) Binary, Octal
b) Octal, Binary
c) Hexadecimal, Binary
d) Binary, Hexadecimal
Answer: c
Clarification: Since, 2⁴ = 16, therefore, the decoder can act as hexadecimal to binary converter. Because, 4 bits input is converted to 16 bits output. Each bit corresponding to 4 output bits. So, clearly it is a hexadecimal to binary convertor.

10. Following entity may represent a ________ circuit.

ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
              x    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              y    : OUT STD_LOGIC);
END my_circuit;

a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adder
Answer: d
Clarification: The entity gives information about inputs and outputs of the circuit. The circuit has two inputs and both are of vector type. There is one vector output and another single bit output. Therefore, it has to be an adder, but because 4 bits are there in the input and output so it is a 4-bit parallel adder.