Category: VHDL Objective Questions

This set of VHDL Interview Questions and Answers for freshers on “Operators – 2”.

1. SIGNAL x : STD_LOGIC; In this statement x is ______
a) Variable
b) Identifier
c) Name
d) Literal
Answer: b
Clarification: Identifier is a simple name given to any constant, variable, signal, entity, port or a subprogram. A name must begin with alphabetic letter. It may contain alphanumeric characters and underscore sign. Reserved words of VHDL can’t be used as identifiers.

2. What is the use of shift operators?
a) To shift the data
b) To shift the identifiers
c) To shift the operators
d) To shift the STD_LOGIC_VECTOR
Answer: a
Clarification: Shift operators are used to shifting of data. These operators were introduced in the VHDL93.

3. What is the “SLL” operator?
a) Shift Logic Left
b) Shift Logically
c) Shift Left Logical
d) Shift Left
Answer: c
Clarification: SLL is a shift operator used to shift bits of the operand to one left position and fills the rightmost position with zero. Shift Left Logical(SLL) operator will shift the bits logically. For example, we had data 0100 in the operand, then after applying SLL, we will get 1000.

4. The correct syntax for any logical shift operator like SLL and SRL is_____
a) bit_vector_operand integer_operand
b) integer_operand bit_vector_operand
c) std_logic_operand integer_operand
d) integer_operand std_logic_operand
Answer: a
Clarification: SLL and SRL operators can shift the operands of vector type. It may be BIT_VECTOR type or STD_LOGIC_VECTOR type. The left operand is shifted towards left or right depending on the operator with number of shifts represented by right operand which always must be an INTEGER type.

5. Refer to the VHDL code given below, what should be the output of the identifier ‘y’ and ‘z’?

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRL 2;
z := x SLL 2;
…

a) y = 0100 and z = 0100
b) y = 0010 and z = 0100
c) y = 0100 and z = 1000
d) y = 0010 and z = 1000
Answer: d
Clarification: SRL operator will shift the operand towards right and SLL will shift the same towards left. All the left bits will be filled with zero in SRL operation and in SLL right bits will be filled with zero. Therefore, y must be x shifted towards right with 2 positions.

6. In the following VHDL code, the values of y and z are _____

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRA 2;
z := y SLA 2;
…

a) y = 0000 and z = 0000
b) y = 1001 and z = 0000
c) y = 1110 and z = 0111
d) y = 0111 and z = 1110
Answer: c
Clarification: SRA and SLA expands to Shift Right Arithmetically and Shift Left Arithmetically respectively. These operators shift the left operand towards right or left by number of bits specified by right operand. Unlike SLL and SRL, the empty bits are not filled with zero, but they are replaced with the MSB in case of SRA and with LSB in case of SLA. For example, in above code, if we shift the x towards right arithmetically then it will become 1100, i.e. the MSB is replicated instead of zero. Therefore, Shifting to two positions will give y = 1110 and z= 0111.

7. SLL operation is equivalent to which of the following operations?
a) Multiplication by any natural number
b) Multiplication by 2
c) Division by 2
d) Exponential operation
Answer: b
Clarification: Shift Left Logical shifts the bits towards left and Shift Right Logical shifts towards right. In binary number system, shifting left refers to multiplication with two and similarly, shifting right refers to division by two. For example, the number 0010 represents 2 in decimal number system. Now, if we shift it left by one position then it will become 0100 which is equivalent to 4 in decimal number system. Therefore, shifting left is equivalent to multiplication operation.

8. Which of the following is equivalent division by 2 operator?
a) SRL
b) SLL
c) SLA
d) SRA
Answer: a
Clarification: SRL operator shifts the given operand towards right. For, example, if we have a number 0010, equivalent to two, which is shifted right then it will become 0001 which is equivalent to 1. Therefore, this operation corresponds to division of any number by two.

9. In the VHDL code given below, what will be the values of y and z?

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x ROR 2;
z := y ROL 2;
…

a) y = 0100 and z = 0000
b) y = 0000 and z = 0000
c) y = 0111 and z = 1110
d) y = 0110 and z = 0110
Answer: d
Clarification: ROR and ROL are Rotate Right and Rotate Left operators respectively. These operators’ wraps around the operand that means the bit shifted out will replace the vacant bit. Therefore, Rotating x two times towards right will give 0110 in y and when it is rotated left then it will be the same.

10. In a statement containing two or more operators of same precedence, how the expression will be solved?
a) Left to right
b) Right to left
c) Alphabetically
d) In a random manner
Answer: a
Clarification: In VHDL, to solve any expression a simple rule is followed. The rule is “highest precedence first, left to right within same precedence”. However, we can use parenthesis to control the order of operations, but by default it will solve left to right. It may be noted that parenthesis is the operator with highest precedence.

11. What will be the values of the following variables after MOD operations?

x = 5 MOD 3;
y = -5 MOD 3;
z = 5 MOD -3;

a) x = 2, y = -2 and z = -2
b) x = 2, y = 1 and z = -2
c) x= 2, y = -2 and z = 2
d) x = 2, y = -2 and z = 1
Answer: b
Clarification: MOD takes the sign of divisor which is the second operand, but not of first operand. In the first operand, it will simply give the remainder which is 2. In the second statement, the modulo will not contain negative, it will simply divide and the result will be 1. This is done by adding 3*2 in -5, in that case 1 is left, therefore modulo is 1. But, in third statement, divisor is negative so it will be taken as -(5 MOD 3).

12. What will be the values of following variables after REM operations?

x = 5 REM 3;
y = -5 REM 3;
z = 5 REM -3;

a) x= 2, y = 1 and z = -2
b) x = 2, y = -2 and z = 1
c) x = 2, y = -2 and z = 2
d) x = 2, y = 1 and z = 1
Answer: c
Clarification: Here, REM operator is used, which takes the sign of dividend instead of divisor unlike MOD operator. In case of negative divisor, the sign is ignored. Therefore, in first statement, the remainder is calculated normally, which is 2. In second statement, it will be considered as -(5 REM 3). In third statement, it is simply solved like first statement, ignoring the negative sign.

13. XNOR is a logical operator in VHDL.
a) True
b) False
Answer: a
Clarification: XNOR is a logical operator representing Ex-NOR operation and was introduced in VHDL 93. In the previous versions, there was no XNOR operator and to perform Ex-NOR, we needed to implement it by using XOR itself.

VHDL for Interviews, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “LOOP Statement – 1”.

1. A loop statement is used where we needs to ________
a) Select one from many choices
b) Check a condition
c) Repeat the statements
d) Choose one from two cases
Answer: c
Clarification: As the name suggests, a loop statement includes a sequence of statements which have to be executed repeatedly zero or more times. There are different iteration schemes available to generate loops in which some condition may be included to generate a finite loop.

2. Loop is a ________ statement.
a) Concurrent
b) Sequential
c) Assignment
d) Functional
Answer: b
Clarification: Like IF, WAIT, CASE, LOOP is also intended exclusively for sequential code. It is a sequential statement which can be used inside a process, function or procedure only.

3. How many styles of loop statement does the VHDL have?
a) 2
b) 3
c) 4
d) 5
Answer: a
Clarification: There are two different styles of the loop statement which are FOR LOOP and WHILE LOOP. These are called the iteration schemes. However, it is possible to define a loop without using these iteration schemes. In that case we need to use WAIT statement.

4. What is the use of FOR loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false
Answer: a
Clarification: FOR LOOP iteration scheme is used to repeat the statements enclosed within a fixed number of times. There is no condition used in the for loop, but a limit is set which must be static and the loop will run only given number of times.

5. Which of the following is correct syntax for defining FOR LOOP?
a)

    label : FOR LOOP loop_specification
     sequential_statements;
     ….
     END LOOP label;

b)

    label : FOR loop_specification LOOP
     sequential_statements;
     ….
     END FOR LOOP;

c)

    label : FOR LOOP loop_specification
     sequential_statements;
     ….
     END FOR LOOP;

d)

    label : FOR loop_specification LOOP
     sequential_statements;
     ….
     END LOOP label;

View Answer

Answer: d
Clarification: The FOR LOOP is defined by using an optional label followed by a keyword FOR. After which the specification is defined which is the number of times loop should execute. This specification is followed by keyword LOOP. After this we can start writing sequential statements and the loop is ended with END LOOP and an optional label.

6. What is the use of WHILE loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false
Answer: b
Clarification: WHILE LOOP is repeated until a condition no longer holds. The condition is first tested and if it is found to be true then the loop iteration starts. With the end of iteration, the condition is again tested and the process continues until the condition is not false.

7. Which of the following is correct syntax for WHILE LOOP?
a)

   label: WHILE LOOP specification IS
    sequential_statements;
    END LOOP;

b)

    label: WHILE LOOP condition
    sequential_statements;
    END LOOP label;

c)

    label: WHILE condition LOOP
    sequential_statements;
    END LOOP label;

d)

   label: WHILE specification LOOP
    sequential_statements;
    END LOOP;

View Answer

Answer: c
Clarification: WHILE loop can be declared by using an optional label followed by the keyword WHILE. After writing WHILE, the condition must be written, the loop will execute until the condition will be true. Otherwise, the loop will not execute.

8. What does the next statement in loops do?
a) Skips the current iteration
b) Starts the next loop by ending the current
c) Exits the loop
d) Skips the next line of the loop
Answer: a
Clarification: The next statement is used to skip the current iteration and start the next iteration of the same loop. This statement passes the control the statement which is enclosing the innermost loop. This statement is useful when one needs to perform some action for every value except one.

9. What is the syntax to use the NEXT statement?
a) NEXT condition loop_label
b) NEXT loop_label WHEN condition
c) loop_label NEXT WHEN condition
d) loop_label NEXT condition
Answer: b
Clarification: The next statement can be used by using the keyword NEXT followed by the loop label so that it can execute the next iteration by passing the control to the statement containing loop_label. Loop label is followed by keyword WHEN and one condition so that the iteration is skipped only when the condition is true. If there is no label given to the loop then there is no need to write the label in the NEXT statement. In that case, next statement applies to the innermost enclosing loop.

10. It is not possible to write an infinite loop in VHDL.
a) True
b) False
Answer: a
Clarification: Since VHDL is a hardware description language, so unlike traditional programming languages we can’t write an infinite loop. Actually PROCESS itself is an infinite loop that executes whenever any signal of sensitivity list changes. It is necessary to add some exit statement or a condition in every loop.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Value Kind Attributes”.

1. What does a value kind attribute return?
a) A single value
b) A signal
c) A function
d) A type
Answer: a
Clarification: Value kind attributes to return a single value. This value can give information about anything like an array, a block or a type. This can be used to return the length of an array or some related information.

2. Value attributes are classified into _______ subclasses.
a) 1
b) 2
c) 3
d) 4
Answer: c
Clarification: Value kind attributes are further broken down into three subclasses. This classification is done on the basis of the information they provide. For example, if an attribute is providing the information about an array then it is called Value array attribute.

3. Which of the following is not a category of Value kind attribute?
a) Value type attributes
b) Value array attributes
c) Value block attributes
d) Value function attributes
Answer: d
Clarification: The Value kind attributes are divided into three categories which are Value type attributes (which returns the value of a type), Value array attributes (information about array) and Value Block attributes (information about block).

4. If T is an object, then T’LEFT attribute returns ________
a) Upper bound of object
b) Leftmost value of object
c) Leftmost value of an array
d) Lower bound of the object
Answer: b
Clarification: T’LEFT is an attribute which returns the left bound or the leftmost value of the object T. This object can be any predefined type, array or any block as well. Similarly, T’RIGHT returns the rightmost value of array.

5. What does the attribute T’HIGH returns?
a) Upper bound of the object
b) Lower bound of the object
c) Highest value of the object
d) Rightmost value of the object
Answer: a
Clarification: T’HIGH is another value kind attribute which gives information about the type, array or block. It returns the upper bound of the type or array. In a similar manner T’LOW will returns the lower bound of the object T.

6. What will be the value of x and y?

TYPE my_type IS ARRAY (15 DOWNTO 0) OF BIT;
…
VARIABLE x, y : INTEGER;
x := my_type’LEFT;
y := my_type’HIGH;
…

a) 0, 0
b) 0, 15
c) 15, 0
d)15, 15
Answer: d
Clarification: Since the attribute used is for the type, so it is value type attribute. ‘LEFT will give the left bound of the type or the leftmost value which is 15. Here my_type is described as a data type which has bound 0 to 15. So, HIGH will return the upper bound which is 15. So, x and y both will be 15 in this case.

7. What will be the value of x and y in the code given below?

TYPE bit_range IS ARRAY (0 TO 15) OF BIT;
VARIABLE x, y : INTEGER;
x := bit_range’RIGHT;
y := bit_range’LOW;
…

a) 0, 0
b) 0, 15
c) 15, 0
d) 15, 15
Answer: c
Clarification: T’RIGHT returns the rightmost value of any type. So, x will be 15. Similarly, T’LOW retruns the lower bound of the same. Here the bounds of the array are 0 and 15 as lower and upper bound. So, the resulting value of y will be 0.

8. What will be the type of value returned by the attribute T’LENGTH?
a) BIT
b) INTEGER
c) STD_LOGIC
d) BOOLEAN
Answer: b
Clarification: T’LENGTH is a Value Array attribute which returns the length of array. For example, if an array has 32 elements, then it will return 32. So, T’LENGTH returns a value of integer type.

9. What will be the value of my_array’LENGTH, if my_array is defined as below code?

TYPE my_array IS ARRAY (15 DOWNTO 0) OF STD_LOGIC;

a) 15
b) 16
c) 0
d) 32
Answer: b
Clarification: Since, T’LENGTH returns the length of object T. So, my_array’LENGTH will return the length of my_array. Here, my_array has 16 elements from 0 to 15, so the value returned by ‘LENGTH attribute will be 16.

10. The formula for T’LENGTH is best described by which of the following?
a) T’HIGH – T’LOW + 1
b) T’HIGH – T’LOW
c) T’HIGH + T’LOW – 1
d) T’HIGH + T’LOW
Answer: a
Clarification: T’HIGH will return the upper bound of the array and T’LOW will return the lower bound of the array. Also, the number of elements in an array is given by upper bound – lower bound + 1. Therefore, option a describes the formula best.

11. Which of the following is the return type of value T’ASCENDING?
a) Bit
b) Integer
c) Boolean
d) Same as T
Answer: c
Clarification: Ascending is a value kind attribute which can take two values either TRUE or FALSE. Regardless of type of the object T, the value returned by attribute ‘ASCENDING is always of Boolean type.

12. For which of the following declarations, the value returned by ‘ASCENDING attribute will be true?

TYPE array_1 IS ARRAY (0 TO 31) OF BIT;
TYPE array_2 IS ARRAY (15 DOWNTO 0) OF BOOLEAN;

a) For array_1 only
b) For array_2 only
c) For both array_1 and array_2
d) Neither for array_1 nor for array_2
Answer: a
Clarification: The T’ASCENDING will return true only if the array T is defined as in an ascending order. For example, areay_1 is defined from 0 to 31 whereas array_2 is defined from 15 to 0. Therefore, in case of array_1, the value will be true.

13. Which of the following attribute is available for all types?
a) ‘LEFT
b) ‘ASCENDING
c) ‘BASE
d) ‘HIGH
Answer: c
Clarification: ‘BASE is an attribute available for all the types, May it be a predefined data type or user defined data type. It returns the base type of the object. The type of object must have some base type which is returned by attribute.

14. What kind of information is provided by the value block attributes?
a) About the block name
b) About the modeling of block
c) About the architecture name
d) About the inputs used in block
Answer: b
Clarification: Value block attributes returns information about how a block in a design is modeled. For example, whether the structural modeling is used or behavioral modeling is used within a block or architecture.

15. Which of the following returns TRUE if there is no component instantiation statement in the block?
a) ‘STRUCTURE
b) ‘BLOCK_COMPONENT
c) ‘BLOCK_BEHAVIOUR
d) ‘BEHAVIOR
Answer: d
Clarification: ‘STRUCTURE and ‘BEHAVIOR are two predefined attributes that are under the category Value block. Both of them return true value. ‘BEHAVIOR will return true if there is no component declaration and instantiation inside the block to which it is attached. However, ‘STRUCTURE performs exactly opposite.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Asynchronous Preset and Clear”.

1. What type of inputs is preset and clear?
a) Data input
b) Output
c) Clock input
d) Control input
Answer: d
Clarification: Preset (PRE) and clear (CLR) are asynchronous control inputs, which means output responds to these inputs immediately because they have control over the output that is because they are not synchronized by an external clock.

2. Clear (CLR) or preset (PRE) with a bar above them shows that they have ________
a) Active high input
b) Active low input
c) Clocked input
d) No input
Answer: b
Clarification: The inversion bar over the designations of preset and clear shows that they have active LOW asynchronous inputs. If the preset input is active low, then the output of the flip-flop is set to one. If the clear input is active low, then the output of the flip-flop is reset to 0.

3. Asynchronous inputs are also called override inputs.
a) True
b) False
Answer: a
Clarification: Asynchronous inputs change the state of the flip-flop regardless of the clock input, they override inputs which can force a particular state onto the flip-flop that’s why they are also called override inputs.

4. The output of the flip-flop _______ when both the input, preset and clear are active low at the same time.
a) Is set to 1
b) Is set to 0
c) Becomes X (Don’t care)
d) Is controlled by clock
Answer: c
Clarification: If preset is active low then Q=1, Q’=0. If clear is active low Q=0, Q’=1. It is not possible to preset and clear a flip-flop at the same time because Q can’t be 0 and 1 at the same instant of time, hence the output of the flip-flop will become X, which is don’t care.

5. What is the state of PRESET input?
a) Reset
b) Set
c) Invalid
d) Don’t care
Answer: b
Clarification: After the preset input is activated, the flip-flop will be SET i.e. Q=1 and Q’=0 without considering any synchronous input or clock input. So the state of the preset input is set.

6. What is the state of CLEAR input?
a) Reset
b) Set
c) Invalid
d) Don’t care
Answer: a
Clarification: After the clear input is activated, the flip-flop will be RESET i.e. Q=0 and Q’=1 without considering any synchronous input or clock input. The flip-flop will go back to its initial state.

7. What happens if both the inputs PRE and CLR are activated?
a) Flip-flop is reset
b) Flip-flop is set
c) Invalid State
d) No output
Answer: c
Clarification: If preset input and clear input both are activated in the flip-flop then, Q and Q’ go to the same state simultaneously which is not possible. Hence, then flip-flop gives an invalid state as the output.

8. Which of the following input on a flip-flop has control over the outputs?
a) Data input
b) Clock
c) Enable
d) Preset
Answer: d
Clarification: Preset is an asynchronous input, it has the control over the output while synchronous inputs have control over the output ONLY in step, or in sync with the clock signal transitions.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Behavioural Modelling”.

1. The most basic form of behavioral modeling in VHDL is _______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
Answer: b
Clarification: Assignment statements are used basically in the behavioral modeling. In behavioral modeling, one needs to describe the value of outputs for various combinations of inputs, so we need to assign different values to output variables. Therefore, the assignment is the most used statement in behavioral modeling.

2. For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
Answer: d
Clarification: A concurrent assignment statement assigns the value of right operand to left operand and this statement is executed many times. Whenever the value of right operand is changed, the assignment statement is executed.

3. a < = b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.
a) True
b) False
Answer: a
Clarification: The keyword ‘after’ is used for introducing delay in the assignment statement. Whenever the value of b is changed, the value of a is changed after 10ns. This 10ns is helpful while creating square waveform.

4. Which of the circuit is described by following VHDL code?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_func IS
PORT(x, a, b : IN std_logic;
q : OUT std_logic);
END my_func;
ARCHITECTURE behavior OF my_func IS
SIGNAL s : INTEGER;
BEGIN
WITH s SELECT
q <= a AFTER 10 ns WHEN 0;
         b AFTER 10 ns WHEN 1;
s <= 0 WHEN x = ‘0’ ELSE
        1 WHEN x = ‘1’;
END behavior;

a) AND gate
b) OR gate
c) MUX 2:1
d) DEMUX 1:2
Answer: c
Clarification: In this code, the behavior of 2:1 MUX is explained. By using WITH statement, the output is selected by the use of select line. Here, s is used as select line and x is considered as the value of select line. Also, a and b are taken as two inputs and q as output.

5. The main problem with behavioral modeling is ________
a) Asynchronous delays
b) Simulation
c) No delay
d) Supports single driver only
Answer: a
Clarification: In behavioral modeling, there are different types of delays and this can create problem in functioning of system. Sometimes zero delay events are used to produce consistent results. If these are not properly ordered, results can be disparate between different simulations.

6. What is the use of simulation deltas in VHDL code?
a) To create delays in simulation
b) To assign values to signals
c) To order some events
d) Evaluate assignment statements
Answer: c
Clarification: Simulation deltas are used to order some specific events to avoid complications in simulations. Especially, in zero delay events, they are properly ordered so as to produce consistent results. It is actually a complex delay model used for zero delay events.

7. VHDL can’t handle multiply driven signals.
a) True
b) False
Answer: b
Clarification: A multiply driven signal is the one which has more than one driver. VHDL can handle these signals easily and in a unique way. These multiply driven signals are useful for modeling various data bus and bidirectional bus etc.

8. Which function is used to create a single value for multiple driver signals?
a) Resolution function
b) Package
c) Concurrent assignments
d) Sequential assignments
Answer: a
Clarification: The values of all the drivers are resolved together to create a single value for the signal. The method of resolving all the drivers is through a resolution function which is a designer writer function. That function is called whenever any one of the driver changes its value.

9. Refer to the VHDL code given below, which of the following signal is driven by multiple drivers?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY function IS
PORT (b, c : IN BIT;
a, d : OUT BIT);
END function;
ARCHITECTURE behavior OF my_func IS
BEGIN
a <= b;
a <= c;
d <= b;
END behavior;

a) d
b) c
c) b
d) a
Answer: d
Clarification: A signal is called multiply driven signals if it is driven by more than one signals or the value of signal changes with respect to more than one signal. Here, the value of changes when the value of b or value of c changes. Therefore, a is driven by two drivers named as b and c. Each concurrent statement creates a driver for left operand.

10. A signal is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?
a) By short circuiting both driver
b) By open circuiting one driver
c) By AND operation between two drivers
d) By NOT operation of both drivers
Answer: a
Clarification: The value of multiple driver signal is found by using resolution function. The default resolution function short circuits all the drivers and performs OR operation which means any change in any driver will cause change in output signal. The value of delays is also taken into consideration.