Category: VHDL Objective Questions

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Common Terms used in VHDL”.

1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
Answer: b
Clarification: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.

2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Answer: c
Clarification: Package is a collection of all the commonly used data types and subroutines so that programmers can easily use them in their design without defining the same functions again and again.

3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
Answer: a
Clarification: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.

4. An entity can have more than one architecture.
a) True
b) False
Answer: a
Clarification: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.

5. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Answer: d
Clarification: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.

6. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
Answer: a
Clarification: Bus is a special kind of signal. It may have its drivers turned off.

7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
Answer: b
Clarification: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.

8. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
Answer: d
Clarification: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.

9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
Answer: c
Clarification: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.

10. A process is the basic unit of execution in VHDL.
a) True
b) False
Answer: a
Clarification: All the operations in the VHDL description are divided into processes during simulation and therefore, Process is the basic unit of execution.

11. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Answer: a
Clarification: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.

12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
Answer: b
Clarification: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.

13. Which of the following is used at the end of a statement?
a) ; (Semicolon)
b) — ( double hyphen)
c) _ (underscore)
d) No sign is used at the end of statement
Answer: a
Clarification: Semicolon is the sign used at the end of any statement. Double hyphen is used for writing a comment which means wherever we have a sign of double hyphen(–), the simulator will skip that line and start compiling from the next line.

14. Which of the following is correctly declared library for VHDL code?
a)

LIBRARY library_name;
USE package_name.parts;

b)

LIBRARY package_name.parts;
LIBRARY library_name;

c)

USE library_name;
LIBRARY library_name.package_name.parts

d)

LIBRARY library_name;
USE library_name.package_name.parts

View Answer

Answer: d
Clarification: Library declaration is completed in two lines. First line declares the library and in second line we use ‘USE’ clause to define the package name we want to use from the respective library and the parts we want to use. For example, LIBRARY ieee; USE ieee.std_logic_1164.all; In this declaration, ieee is library and std_logic_1164 package is used; all in package part section specifies that all parts of package are used.

15. One can’t use more than one library in the VHDL code.
a) True
b) False
Answer: b
Clarification: There is no restriction on the number of libraries we want to use. One can define more than one library in VHDL code.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Signal Assignment – 1”.

1. The signal assignment is considered as a ________
a) Concurrent statement
b) Sequential statement
c) Subprogram
d) Package declaration statement
Answer: a
Clarification: The signal assignment statement is typically considered a concurrent statement rather than a sequential statement. However, the statement can be used as a sequential statement as well but has a side effect of obeying the general rules for when the left operand is actually updated.

2. How can we use an assignment statement as a sequential assignment?
a) By using keyword WAIT
b) By using a delay mechanism
c) By using conditional statements
d) By using it in any process
Answer: d
Clarification: The assignment statements can appear either in architecture or in a process. According to this only, the signal assignment is classified as a concurrent and sequential assignment. If the signal assignment is done in a process, then it is a sequential assignment, otherwise it is a concurrent assignment.

3. The sequential assignment statement is activated, whenever ________
a) The waveform associated changes its value
b) The process is terminated
c) The execution is scheduled
d) The value of the target is needed
Answer: b
Clarification: The sequential assignment statement appears inside a process. The statements inside the process are sequential statements and the assignment is activated when the process ends. So, the assignment will take place at the time of process termination only.

4. The concurrent assignment statement is activated whenever ______
a) The execution is scheduled
b) The value of the target is needed
c) The waveform associated changes its value
d) The process is terminated
Answer: c
Clarification: Concurrent assignment statement has nothing to do with processes. It is executed whenever the waveform associated with it changes its value. The value of the target is updated every time the value of waveform changes.

5. Which of the following is correct syntax for a signal assignment statement (if {} specifies an optional part)?
a) target <= {delay_mechanism} waveform;
b) target <= delay_mechanism waveform;
c) target <= delay_mechanism {waveform};
d) target <= {delay_mechanism} {waveform} value;
Answer: a
Clarification: The proper signal assignment is shown in option target <= {delay_mechanism} waveform;. The ‘target’ gets the value of ‘waveform’ by executing the delay mechanism. The delay mechanism is ,however, optional but is used most of the times for better timing performance of the circuit.

6. The conditional assignment statement is a _________ assignment.
a) Sequential
b) Concurrent
c) Selected
d) None of the above
Answer: b
Clarification: The conditional statement is a type of concurrent assignment statement in which the assignment is executed only if the condition specified is true. It may be noted that the condition is Boolean i.e. it may have only two values true or false.

7. Sequential assignments are synthesizable.
a) True
b) False
Answer: a
Clarification: Generally, sequential assignments are synthesizable by EDA tools. The assignment statement must be using some operators and types. The only case when these assignments are not synthesizable is when the types and operators are acceptable to the synthesis tools.

8. Delays are generally ignored in ________ assignments statements.
a) Concurrent
b) Conditional
c) Sequential
d) Selected
Answer: c
Clarification: Conditional and selected assignments are type of concurrent assignment. In case of concurrent assignments delays are usually taken into consideration. Whereas, there is no use of delays in sequential assignments since it is executed at the end of process. So, there is no need for delay in sequential assignments.

9. Which of the following can’t be a mode for target operand of assignment statement?
a) BUFFER
b) INOUT
c) OUT
d) IN
Answer: d
Clarification: The left operand of assignment statement, called the target operand is always assigned the value of another operand. There is no chance of using IN type target on the left side of an assignment statement. It is mandatory that the direction of target include output.

10. Which of the following is a variable assignment statement?
a) <=
b) :=
c) =>
d) ==
Answer: b
Clarification: To assign a value to variable, a variable assignment statement is used. The symbol used for variable assignment is ‘:=’ whereas when we assign some value to a signal, <= statement is used. In case of variables if we use <= instead of :=, there can be some problem with the delay mechanisms.

11. Which of the following is a keyword used for conditional assignment?
a) IF
b) WHEN
c) FOR
d) END
Answer: b
Clarification: Conditional statement is an assignment statement in which a condition is first tested and then assignment occurs. It uses the keyword WHEN to assign value to a signal conditionally. For example, y <= ‘1’ WHEN x = ‘0’. This is a conditional statement that will assign value 1 to signal y only when signal x is low.

12. For a signal used in sequential assignment, it can have _______ driver(s).
a) 1
b) 2
c) 3
d) 4
Answer: a
Clarification: Sequential assignment statement is the one that is used in a process. This statement is executed at the end of the process. No matter how many signal assignment statements are used, only the last one is taken into consideration(for 1 signal). So, in a process, one signal can have only 1 driver.

.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Some Predefined Packages”.

1. Which of the following package need not to be a part of the VHDL code?
a) STANDARD
b) STD_LOGIC_1164
c) TEXTIO
d) STD_LOGIC_ARITH
Answer: a
Clarification: The package STANDARD is usually integrated directly in the simulation or synthesis program. Therefore, it doesn’t exist as a VHDL description. It doesn’t have to be explicitly included by the USE clause.

2. In which of the following library, the package STANDARD defined?
a) IEEE
b) STD
c) WORK
d) STD_LOGIC
Answer: b
Clarification: The package STANDARD is a part of STD library which doesn’t need to be included in the code. It is automatically included in the description without any extra statement or declaration. All other packages of STD library needs to be defined in the code itself.

3. Which of the following is not defined in the STANDARD package?
a) Basic data types
b) Functions for different operations for data types
c) Functions to read from the text files
d) Functions for arithmetic operators
Answer: c
Clarification: The package STANDARD contains all the basic data type like Boolean, bit, bit_vector, integer, character and so on. It also contains logical, comparison and arithmetic operators for these data types. It doesn’t contain any function to read and write into text files.

4. Which statement is correct to include a package in the code where we need to read from and write to text files?
a) USE STD.TEXT.all;
b) USE STD.TEXTIO.all;
c) USE IEEE.TEXTIO.all;
d) USE IEEE.TEXT.all;
Answer: b
Clarification: The package which contains procedures and functions needed to read from and write to text files is the TEXTIO package. This package is defined in STD library of the VHDL. So, the correct statement is USE STD.TEXTIO.all to include the TEXTIO package.

5. TEXTIO package is included in the code by default.
a) True
b) False
Answer: b
Clarification: It is not true that TEXTIO package is included in the code by default. However, it is defined in the STD library from which STANDARD and such packages are included by default but this is not the case with TEXTIO package. It needs the USE clause to be included in the package.

6. Among the four packages given below, which is the most used package of VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STD_LOGIC_ARITH
d) NUMERIC_STD
Answer: a
Clarification: The STD_LOGIC_1164 package is most used package in VHDL since it contains definition of data types which are used for modeling wires at the time of synthesis. To use such data types, it is necessary to include STD_LOGIC_1164 in the code. In fact, it is used in almost every single design in VHDL.

7. The STD_LOGIC_1164 package is contained by _______ library.
a) STD
b) WORK
c) STD_LOGIC
d) IEEE
Answer: d
Clarification: The STD_LOGIC_1164 package has been developed and standardized by the IEEE and hence it is included in IEEE library of VHDL. It could be referenced easily by using two statements: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; Also, this is not included by default.

8. What is the most important use of STD_LOGIC_1164 package?
a) To define and use parallel operations
b) To use concurrent code
c) To use sequential code
d) Multi value logic system
Answer: d
Clarification: STD_LOGIC_1164 defines the data types like STD_LOGIC, STD_ULOGIC and the corresponding vector types. These data types basically work on multi valued logic system rather than two valued logic (0, 1). So, to use this multi value logic we need to include the STD_LOGIC_1164 package.

9. Which package defines the data type STD_LOGIC_SIGNED?
a) STD_LOGIC_1164
b) STD_LOGIC_ARITH
c) STD_LOGIC_NUMERIC
d) IEEE
Answer: b
Clarification: SRD_LOGIC_ARITH is another package defined in the IEEE library. This package gives a definition of STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED data types. The basic purpose of STD_LOGIC_ARITH is to provide arithmetic accessibility to STD_LOGIC data types etc.

10. What is another name for STD_LOGIC_ARITH package?
a) STD_LOGIC_1164
b) STD_LOGIC_NUMERIC
c) NUMERIC_STD
d) ARITH_STD
Answer: c
Clarification: STD_LOGIC_ARITH is basically provided by Synopsys and NUMERIC_STD is provided by IEEE. Both of the packages are equivalent and define the same arithmetic functions. So, STD_LOGIC_ARITH is another name for NUMERIC_STD package.

11. The basic arithmetic function provided by STD_LOGIC_ARITH is for ______ data type.
a) STD_LOGIC_VECTOR
b) STD_LOGIC
c) INTEGER
d) CHARACTER
Answer: a
Clarification: STD_LOGIC_ARITH basically contain arithmetic functions to enable calculations and comparisons based on the types STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR. So, calculations related to vector types of STD_LOGIC_1164 are in STD_LOGIC_ARITH package.

12. The following statement must be in _______ package.

TYPE my_type IS RANGE (0, 1);

a) STD_LOGIC_1164
b) STANDARD
c) STD_LOGIC_ARITH
d) IEEE
Answer: b
Clarification: Since the data type my_type can have only two values which are 0 and 1 which is the case of BIT data type. Therefore, my_type is BIT data type which is defined in STANDARD package. So, the given statement must be in STANDARD package.

13. Which of the following package may contain the given statement?

TYPE color IS RANGE (red, green, blue, black)

a) STD_LOGIC_1164
b) STANDARD
c) STD_LOGIC_ARITH
d) WORK
Answer: d
Clarification: There is no such pre defined data type which may take any value like red, green, blue or black. So, this must be a user defined data type and not a predefined one. Therefore, it must be defined in WORK package.

14. Following lines are a part of _______ package.

TYPE my_type IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘ L’, ‘H’, ‘-‘);

a) STANDARD
b) STD_LOGIC_ARITH
c) STD_LOGIC_1164
d) WORK
Answer: c
Clarification: The given type shows 9 valued logic which is STD_ULOGIC type having 9 different values. This multi valued logic is defined in STD_LOGIC_1164 package of IEEE library. Apart from STD_ULOGIC, STD_LOGIC is also defined in STD_LOGIC_1164.

15. In STD_LOGIC_1164, the resolution function for ______ is not provided.
a) STD_LOGIC
b) STD_LOGIC_VECTOR
c) STD_ULOGIC
d) STD_ULOGIC_VECTOR
Answer: c
Clarification: STD_ULOGIC is the unresolved data type of the STD_LOGIC_1164 package. STD_LOGIC is the resolved version of STD_ULOGIC. Similarly, there are resolution functions to resolve vector types into scalar types.

This set of VHDL Assessment Questions and Answers on “All Keywords in VHDL – 2”.

1. When the keyword GUARDED is used, it is always mandatory that the statements inside will be executed concurrently.
a) True
b) False
Answer: a
Clarification: Since Guarded is always used with the BLOCK statement which itself is a block statement and contains concurrent statements. So, wherever we are using guarded, it means that the statement will be executed concurrently.

2. Among the following, with which keyword MAP is generally used?
a) IS
b) PORT
c) COMPONENT
d) LABEL
Answer: b
Clarification: MAP is generally used with PORT for mapping of the components. PORT MAP statement is used for instantiation of the component after its declaration is being done.

3. Impure is a type of _______
a) Data type
b) Array
c) Function
d) Component
Answer: c
Clarification: IMPURE keyword is used to define impure functions. An Impure function is a function which can return some different type given that the actual parameters are same.

4. How does keyword inertial affect an assignment statement?
a) By defining initial value from which delay should be started
b) To prevent overriding of following delay assignment statements
c) To specify wire delay
d) No effect
Answer: d
Clarification: Inertial delay is the default delay in VHDL. If the assignment statement is y <= x AFTER 10 ns; then it will be same as y <= INERTIAL x AFTER 10 ns; There is no difference between two given statements. So, adding inertial doesn’t affect the assignment.

5. Which of the following keyword must be used to specify wire delay?
a) TRANSPORT
b) INERTIAL
c) WIRE
d) DELTA
Answer: a
Clarification: The Transport delay is analogous to the delay incurred by passing a current through a wire and therefore, it is also called wire delay. To specify the transport delay type in an assignment, the keyword TRANSPORT is used.

6. Which of the following is associated with the INOUT keyword?
a) Type of a signal
b) Mode of a signal
c) Name of a signal
d) Function of a signal
Answer: b
Clarification: INOUT is a kind of mode of a signal specified in any entity or architecture. The signal can have four modes- IN, OUT, INOUT and BUFFER. So, INOUT is a mode of signal which is used to specify the signal can be used as input as well as output type.

7. The word LABEL is not reserved in VHDL.
a) True
b) False
Answer: b
Clarification: LABEL is also a reserved word in VHDL. However, we can write the name of label in starting of any specific statement. But, LABEL itself is a reserved word used for specify a label name in an attribute statement.

8. What is LINKAGE keyword associated with?
a) Signals
b) Variables
c) Constants
d) Identifiers
Answer: a
Clarification: LINKAGE keyword is associated with signals in VHDL. It is used to link VHDL ports with non-VHDL ports. This corresponds to the mode of a signal and is used when we need to connect VHDL design to some non-VHDL ports.

9. LINKAGE keyword is same as _______ mode.
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Clarification: LINKAGE is same as INOUT mode of a signal. In case of LINKAGE, we can use the signal as we can use it in INOUT mode. There is no difference between LINKAGE and INOUT modes of a signal.

10. MOD keyword is a ________
a) Data type
b) Literal
c) Operator
d) Function
Answer: c
Clarification: MOD is the modulus operator which can be used on two integer operands. It is actually an arithmetic operator which can be applied to integer types only. It returns the remainder after dividing first operand by the second operand.

VHDL Assessment Questions, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Top Level System Design”.

1. The top-level system design is modelled for functionality and performance.
a) True
b) False
Answer: a
Clarification: In the top-level system design each major component in the design is formed at the gate level and the design is simulated again for the timing, functionality and performance.

2. Which modelling is used in the top-level system design?
a) Low-level behavioural modelling
b) High-level behavioural modelling
c) Structural modelling
d) Data flow modelling
Answer: b
Clarification: High-level behavioural modelling is used in the top-level system design. It is the highest level of abstraction in the VHDL. This level simulates the behavioural level of the circuits and the development rate at this level is highest.

3. What are the two constructs used in most of the behavioural modelling?
a) Assign
b) Begin and end
c) Initial and always
d) Always and end
Answer: c
Clarification: The two constructs used in most of the behavioural modelling are Initial and always. All the other behavioural statements appear only inside these two structured procedure constructs.

4. How many levels of abstraction are there in the top-level system design?
a) One
b) Two
c) Three
d) Four
Answer: c
Clarification: There are three levels of abstraction: algorithm, register transfer level (RTL), and gate level. Algorithms cannot be synthesized, RTL is the input to the synthesis, gate level is the output from the synthesis.

5. Timing performance of design is checked by which of the following simulation mode?
a) Gate-level
b) Behavioural
c) Transistor-level
d) Switch-level
Answer: a
Clarification: Gate-level simulation is used to check the timing performance of a design. It quickly does the implementation of the design and helps in verifying the dynamic behaviour of the circuit which is usually not verified correctly by the static methods.

6. The statements in the initial construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: b
Clarification: The statements in the initial construct constitute the initial block. Initial block is executed only once during the simulation process, at time 0. If there are more than one initial blocks, then all the initial blocks are executed simultaneously.

7. The statements in the always construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: d
Clarification: The statements in the always construct constitute the always block. The always block starts executing at time 0 and keeps on executing during the complete simulation process. It is like an infinite loop.

8. Register data types and memory data types are updated by procedural assignments.
a) True
b) False
Answer: a
Clarification: Procedural assignments update reg, integer, real, time, real-time, and memory data types. The values in procedural assignments change the procedural flow constructs. The variables hold their values until they’re updated by another procedural assignment.

9. How many types of procedural assignments are there?
a) One
b) Two
c) Three
d) Four
Answer: b
Clarification: There are two types of procedural assignments which are blocking and non-blocking assignments. Blocking assignment doesn’t block the execution of the next statement. The non-blocking assignment allows for assignment scheduling.

10. In which order do the blocking assignment statements are executed in a sequential block?
a) Random order
b) Specified order
c) Ascending order
d) Descending order
Answer: b
Clarification: Blocking assignment statements are executed in a SPECIFIED order in a sequential block. The next statement executes only after the present blocking assignments are completed. A blocking assignment doesn’t block the execution of an upcoming statement in a parallel block.

This set of Advanced VHDL Questions and Answers on “Entity and Its Declaration”.

1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals
Answer: d
Clarification: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions.

2. Which of the following can be the name of an entity?
a) NAND
b) Nand_gate
c) Nand gate
d) AND
Answer: b
Clarification: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option b is the only legal word.

3. Which of the following is correct syntax for entity declaration?
a)

ENTITY entity_name IS
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END entity_name;

b)

 ENTITY entity_name
    PORT( signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

c)

ENTITY entity_name IS
    PORT port_name
    ( signal_names : signal_modes signal_type;
    signal_names : signal_modes signal_type);
   END entity_name;

d)

ENTITY entity_name
    PORT port_name
    (signal_names : signal_modes;
    signal_names : signal_modes);
   END ENTITY;

View Answer

Answer: a
Clarification: The correct syntax for declaring an entity block starts with reserve word ENTITY followed by name of entity and the next is reserve word IS. Name of entity can contain letters, numbers and underscore character. After this, PORT declaration is used. PORT declaration is used to declare the interface signals for the entity and to assign mode and type of data. The declaration is completed by using END operator and the entity name.

4. Refer to the VHDL code given below, how many input-output pins are there in MUX entity?

ENTITY mux IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END mux;

a) 5
b) 4
c) 3
d) 2
Answer: c
Clarification: In the given declaration, entity has 3 I/O pins. The signals a and b are Input signals and y is the output signal. So, we can say that the declaration is for 2:1 MUX. In this way, we can find the number of I/O pins from the entity declaration.

5. The entity name ‘xyz’ and ‘XYZ’ will be treated the same.
a) True
b) False
Answer: a
Clarification: VHDL is a strongly typed language which means that there are very strict rules regarding the data types. But, there is no difference between names of entity. VHDL is not case sensitive therefore, ‘xyz’ and ‘XYZ’ are same.

6. Which of the following mode of the signal is bidirectional?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Clarification: INOUT is the only bidirectional mode for any signal. IN, OUT and BUFFER are unidirectional mode since they specifies the type to be either input or output. INOUT can be used as both an input to an entity and as an output of the entity. We can read as well as assign the value for INOUT type signal.

7. In an assignment statement, OUT signal can be used only to the ___________
a) Left of <= operator
b) Right of <= operator
c) Any side of <= operator
d) Right of := operator
Answer: a
Clarification: OUT signal is used to take an output from any entity. Therefore, we can assign it any value but can’t read any value from this type of signal. So, in an assignment statement, OUT type signal can be used on the left side of <= operator.

8. On which side of assignment operator, we can use the IN type signal?
a) Left
b) Right
c) Both
d) Can’t be used
Answer: b
Clarification: IN signal is for input only. We can read the value from IN signal. Therefore, it can be placed only on the right side of assignment.

9. What is the difference between OUT and BUFFER?
a) BUFFER can’t be used inside the entity for reading the value and OUT can be
b) BUFFER can only be read whereas OUT can only be assigned a value
c) BUFFER can be read as well as assigned a value but OUT can only be assigned
d) Both are same
Answer: c
Clarification: BUFFER is a unidirectional mode used as an output from the entity. But, the value of BUFFER can be used inside the entity i.e. it can appear on both sides of assignment operator whereas the value of OUT can’t be used inside the entity and can appear on the left side of assignment operator.

10. GENERICs are not declared in the entity.
a) True
b) False
Answer: b
Clarification: The declaration of GENERICs is also done in the entity itself. It is used to declare the constants that can be used to control the structure of behavior of the entity. The Generics are declared before port declarations.

11. Which of the following is an entity declared for a full adder?
a)

ENTITY full_adder IS
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

b)

ENTITY full_adder IS
    PORT (a ,b : IN BIT;
    s, c : OUT BIT);
    END full_adder;

c)

ENTITY full_adder
    PORT(a, b, c : IN BIT;
    s, co : OUT BIT);
   END full_adder;

d)

ENTITY full_adder IS
    PORT (a, b, c, s, co : BIT);
    END full_adder;

View Answer

Answer: a
Clarification: A full adder has three inputs and two outputs. Inputs are two bits to be added and some carry. Outputs are sum and carry. Therefore, option a shows the correct declaration of entity full_adder. In this, a and b are the bits to be added and c is the input carry whereas, s is the sum output and co is the carry output.

12. How to control the structure and timing of the entity can be changed?
a) By using TIME variable in the entity
b) By changing the entity declaration from time to time
c) By using some special code
d) By using GENERICS
Answer: d
Clarification: The structure and timing constraints can be changed by declaring some constant using GENERICS declaration. For example, in the full adder example, number of bits to be added can be declared as array with its size N. this N can be declared as a constant in the GENERIC declaration part of entity. By changing N only, one can change number of bits for the addition.

13. Which of the following can have more than one driver?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Clarification: INOUT is the only bidirectional signal. This mode can have more than one driver. Therefore, INOUT can be driven by more than one drivers. All other modes like IN, OUT, BUFFER can have only one driver.

14. Which of the following is the default mode for a port variable?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: a
Clarification: IN is the default mode for a port variable. If the mode of any signal is not specified in the port declaration, then it is considered as IN type signal. All other types are needed to be specified at the time of declaration.

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