Category: VHDL Objective Questions

This set of VHDL online test on “WAIT Statements – 2”.

1. Which of the following statement uses only 1 signal?
a) WAIT FOR
b) WAIT UNTIL
c) WAIT ON
d) WAIT UNTIL and WAIT FOR
Answer: b
Clarification: In the case of WAIT UNTIL statement, there can be more than one condition(using logical operators) but all conditions can use the same signal only. WAIT ON, on the other hand, accepts multiple signals. So, if a process has only one WAIT UNTIL statement then it can be concluded that the process is sensitive to only one signal.

2. Given that a process has no sensitivity list and has only one WAIT statement which is WAIT FOR statement. How many signals are there to which process is sensitive?
a) 0
b) 1
c) 2
d) Can’t be determined
Answer: d
Clarification: It is not necessary that we have to write the time value in WAIT FOR statement. One can also use an expression that will be first solved and then the resulting value will be taken as time value. In that case, we can’t say how many signals are used in the WAIT FOR statement. If the time value is directly given then the process has 0 signals in sensitivity list.

3. WAIT statement provides more flexibility than sensitivity list.
a) True
b) False
Answer: a
Clarification: Because the sensitivity list is always written at the starting of the process and this is not true in the case of WAIT statements. They can occur anywhere within the process. Moreover, there can be more than one WAIT statements in the process.

4. Which of the following WAIT statement is most useful for implementing a synchronous sequential circuit?
a) WAIT ON
b) WAIT FOR
c) WAIT UNTIL
d) WAIT TIME
Answer: c
Clarification: WAIT ON statement accepts multiple signals whereas WAIT UNTIL statement can have only one signal. In case of the synchronous sequential circuit there is only one clock signal to which the circuit must be sensitive. Therefore, WAIT UNTIL is most suitable for implementing the synchronous circuits.

5. What is the deadlock condition in VHDL?
a) When WAIT statement keeps on waiting forever
b) When WAIT UNTIL statement uses more than one signal
c) When WAIT ON statement has only one signal
d) When WAIT FOR statement doesn’t have any time clause
Answer: a
Clarification: Deadlock is a condition where a WAIT statement in a process can wait forever. This can happen when two signals are set by other processes and the condition expression can never be true. This condition is called as deadlock condition. To avoid this ASSERT statement can be used to check the continuity of process.

6. In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________
a) At the beginning
b) At the end
c) At the beginning of architecture
d) Where the WAIT statement is encountered
Answer: d
Clarification: WAIT statements are more flexible than sensitivity list and therefore, it can appear anywhere in the process. Wherever the WAIT statement is encountered, the process suspends and waits for any event or condition or a time period depending on the type of WAIT statement. After the condition is met the process continues from the statement next to the WAIT statement.

7. In combinational logic, how many WAIT statements can be used?
a) 0
b) 1
c) 2
d) 3
Answer: b
Clarification: However, process is rarely used to implement combinational logic but, sometimes it is required to use WAIT statement. In that case, only one WAIT statement can be there in the process. Otherwise, it can loop forever during initialization.

8. Refer to the code given below, which kind of circuit is implemented?

PROCESS
BEGIN
WAIT on a, b;
z <= a AND b;
END PROCESS;

a) Combinational
b) Synchronous sequential
c) Asynchronous sequential
d) State machine
Answer: a
Clarification: Since the process doesn’t contain any clock signal therefore, it can’t be a sequential circuit and hence the process is a combinational circuit. Also, there is only one WAIT statement. Therefore, the design must be a combinational circuit.

9. In a procedure is called from a process having a sensitivity list, how many wait statements one can use?
a) 3
b) 2
c) 1
d) 0
Answer: d
Clarification: In any process with a sensitivity list, there can be no WAIT statements. The same is true for any kind of function or procedure called from the process with sensitivity list. So, in any function or procedure called from a process, we can’t use WAIT statement.

all areas of VHDL for online tests, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Configurations”.

1. Configuration is generally associated with ________
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) All of the modeling styles
Answer: c
Clarification: Configurations are generally used to connect component instances to the entity or the external interface. It is basically used with modeling at the component level which is structural modeling.

2. It is necessary to use configuration to bind entity to the architecture in case of structural modeling.
a) True
b) False
Answer: b
Clarification: Configurations are optional and usually are not supported by the synthesis tools. They are used in structural modeling but it is not necessary every time to use a configuration. It makes code more complex.

3. Among the following cases, when the configurations must be used?
a) One entity and two architectures
b) Two entities and one architecture
c) Two entities and no architecture
d) One entity and no architecture
Answer: b
Clarification: The configurations are used when there are multiple number of entities and architectures. To associate one entity with an architecture. For example, there are two different entities defining different ports and an architecture using structural modeling is defining two components with ports in both entities. In that case, configuration can be used to associate the component with a proper entity.

4. Which of the following is correct syntax for defining a configuration?
a)

    FOR instantation_label : component_name
    USE ENTITY library_name.entity_name[(architecture_name)];

b)

    FOR instantation_label : component_name
    USE ENTITY entity_name[(architecture_name)];

c)

    FOR component_name : instantiation_label
    USE ENTITY library_name.entity_name[(architecture_name)];

d)

    FOR component_name : instantiation_label
    USE ENTITY entity_name[(architecture_name)];

View Answer

Answer: a
Clarification: The configuration can be directly defined by using a FOR statement in which the label where the component is instantiated is written first and then the name of component is written. Then a USE clause followed by the name of library in which entity is present to which the component is to be linked. After which the architecture name is written which should be used.

5. Which of the following part is optional in a configuration statement?
a) Instantiation label
b) Library name
c) Entity name
d) Architecture name
Answer: d
Clarification: Architecture name is optional, all other parts are compulsory in a configuration statement. Architecture name is only written if there is more than one architecture associated with the entity then only we have to write architecture name.

6. What is the use of default configurations?
a) To bind the architecture and entity
b) To configure block statements in architecture
c) To bind generics with architecture
d) To bind components with entity
Answer: a
Clarification: When there is no configuration used in structural modeling, then default configuration is used to bind the architecture and entity. Default configuration is associated with entities and architectures. The component is automatically associated with the entity by looking at its ports and modes.

7. Which of the following is true about configurations?
a) To use architecture in configurations, it must be first added to some library
b) A configuration can use more than one architecture for an entity
c) To use an entity in configurations, it must be first added to some library
d) A configuration can’t use any architecture for any entity
Answer: c
Clarification: Since the library name is written before the name of the entity, so it is necessary to add the entity in some library to use it in a configuration. Also, a configuration binds only one architecture with an entity.

8. Apart from the components ________ can also be associated with configurations.
a) Constants
b) Generics
c) Integers
d) Signals
Answer: b
Clarification: Generics can also be defined and attached with the entity by using configurations. Configuration can bind generics and architectures as well. Just like port map and generic map, configurations do the same for these two.

9. It is necessary to define entity and configuration in the same library.
a) True
b) False
Answer: a
Clarification: For any design configuration of some design entity and the configuration itself must be included in the same library. In most cases, the library used is work library, but it is not mandatory to use work every time.

10. Which of the following is not a part of the configuration statement?
a) Architecture specification
b) Instance specification
c) Binding indication
d) Library binding
Answer: d
Clarification: There are always three parts in a configuration statement. First of all architecture is specified by using FOR keyword. Second part is instance specified in which component name followed by instance label is specified. Last part of the statement is a binding indication which specifies the entity name to which architecture should be associated.

11. As a VHDL designer, what should you make sure about the design so that it is synthesized correctly?
a) It must use a configuration when more than one architecture is used
b) All the component ports and entity ports must be matched
c) A configuration must be there always
d) A configuration is used when ports are mismatched
Answer: b
Clarification: Configurations are generally not supported by synthesis tools, so one must ignore them. It should be made sure that all the ports of all components are matching with their counterparts in entities.

This set of Tough VHDL Questions and Answers on “Implementing Combinational Circuits with VHDL – 2”.

1. The process statement used in combinational circuits is called ______ process.
a) Combinational
b) Clocked
c) Unclocked
d) Sequential
Answer: a
Clarification: The process, in which no clock signal is used, is called a combinational process. In a combinational process, the sensitivity list doesn’t include any clock signal for synchronization. In the case of sequential circuits the clock signal is used.

2. Why we need to include all the input signals in the sensitivity list of the process?
a) To monitor the output continuously
b) To monitor the input continuously
c) To make the circuit synthesizable by EDA tools
d) No special purpose
Answer: b
Clarification: If the input signals are not in the sensitivity list of the process, then one can’t monitor the change in input. Any change in input signal will not change the output simultaneously by running the process again.

3. If only two bit vectors are allowed to use in the VHDL code, then how many number of MUX will be required to implement 4 to 1 MUX?
a) 1
b) 2
c) 3
d) 4
Answer: c
Clarification: Since we have inputs with two bits only, so we can use 2 to 1 MUX to implement the required design. So, to design 4 to 1 MUX, we need 3 2 to 1 MUX and hence we can get the desired circuit by using 3 multiplexers.

4. A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement?
a) 2
b) 3
c) 4
d) 5
Answer: d
Clarification: The problem statement says that a 16:1 MUX is to be designed by using 4:1 multiplexers only. This can be done by using 5 numbers of 4 to 1 multiplexers. Here, 4 MUXs are required to collect all the inputs and one is used to select one from the 4 multiplexers outputs.

5. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement?
a) PROCESS(d)
b) PROCESS(d(0), d(1), s)
c) PROCESS(d(0), d(1))
d) PROCESS(d, s, y)
Answer: a
Clarification: In a combinational process, the sensitivity list must include all the inputs. For a 2 to 1 MUX, there must be 2 inputs which are d(0) and d(1); also the process should be sensitive to the select line, so s also should be in the sensitivity list.

6. The given code represents a convertor. Which kind of convertor it is?

ENTITY convert IS
PORT(b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END convert;
ARCHITECTURE convertor OF covert IS
BEGIN
PROCESS(b)
BEGIN
CASE b IS
WHEN “0000” => x <= “1111110”;
WHEN “0001” => x <= “0110000”;
WHEN “0010” => x <= “1101101”;
WHEN “0011” => x <= “1111001”;
WHEN “0100” => x <= “0110011”;
WHEN “0101” => x <= “1011011”;
WHEN “0110” => x <= “1011111”;
WHEN “0111” => x <= “1110000”;
WHEN “1000” => x <= “1111111”;
WHEN “1001” => x <= “1110011”;
WHEN OTHERS => x <= “0000000”;
END CASE;
END PROCESS;
END convertor;

a) Gray to BCD
b) 7 segment to BCD
c) BCD to gray
d) BCD to 7 segment display
Answer: d
Clarification: Clearly, it is a BCD to 7 segment display convertor. This circuit takes a 4 bit BCD input and convert it into 7 bits output which may be used for LED output and hence the 7 segment display can be operated.

7. What is the function of the below code?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;

a) To count number of ones in the given data
b) To count number of zeroes in the given data
c) To reverse the order of given data
d) To perform binary multiplication of two data inputs
Answer: a
Clarification: Because a loop is used and din is monitored for every bit. If any bit in the din is one then the counter is incremented by one. Therefore, the code is counting the number of ones in a given vector of bits.

8. What will be the value of count output, if the data din is 11001111?

ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
             Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;

a) 6
b) 0110
c) 2
d) 0010
Answer: b
Clarification: The count is a signal of bit vector type and hence the output will be a stream of bits. In this case there are 6 ones in the input, which corresponds to 0110 in the binary number system.

9. In the combinational process, the use of output signal in the sensitivity list is illegal.
a) True
b) False
Answer: b
Clarification: Though it is not illegal to use any output signal in the combinational process; but it is not good practice to do. The change in output will cause the process to run again which is not desirable. We can use the output signal in sensitivity list but it will not give desirable results.

10. A parity generator is a combinational circuit and is designed by using a combinational process.
a) True
b) False
Answer: a
Clarification: A parity generator is a combinational circuit since its output depends on the present input only. Also, no clock signal is required to implement and synchronize the parity generator so it can be implemented by combinational process.

Tough questions and answers on all areas of VHDL, .

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Structural Modelling – 1”.

1. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure
Answer: a
Clarification: Structural modeling is the modeling of the circuit at the component level. This type of modeling is used to describe the structure of the system with all the components. Along with components, interconnections between them are also defined.

2. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics
Answer: c
Clarification: A VHDL design can be partitioned in many ways but generics is not the way to partition the design. Generics are used as constants. A component can divide the design at a structural level. Similarly, Blocks and processes can divide the behavioral model of the design.

3. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block
Answer: c
Clarification: Structural modeling describes the design at the component level. Like behavioral modeling is described by using processes, similarly, structural modeling is described by using component instantiation. Both processes and component instantiation are described in the architecture body.

4. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map
Answer: b
Clarification: Component declaration in structural modeling is similar to the entity declaration. It describes the external interface of the component or subcomponent. All the input and output ports are declared in the component declaration part.

5. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design
Answer: a
Clarification: Component instantiation means to use the component in the circuit. Declaration of component just declares the input and outputs of the component but its instantiation describes its interconnection with other components and to port it in the circuit.

6. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit
Answer: b
Clarification: The structural modeling in VHDL is similar to the schematic block diagram of the circuit. Just like block diagram defines the components and interconnection between them, same is the case with structural modeling.

7. Which of the following is correct syntax for component declaration?
a)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END component_name;

b)

     COMPONENT component_name IS
     PORT ( port_mode : type port_name;
     port_mode : type port_name;
     ….);
     END COMPONENT;

c)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END component_name;

d)

     COMPONENT component_name IS
     PORT ( port_name : mode type;
     port_name : mode type;
      ….);
      END COMPONENT;

View Answer

Answer: d
Clarification: To define a component in the code, the keyword COMPONENT is used followed by the name of the component and keyword IS. In the next lines, the ports of the component are declared and the end is done with END keyword followed by the keyword COMPONENT.

8. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP (port_list);
b) label : instantiate COMPONENT PORT MAP (port_list);
c) label : component_name PORT MAP (port_list);
d) label : instantiate component_name PORT MAP (port_list)
Answer: c
Clarification: Component instantiation is done in the architecture part by using some label and the function called PORT MAP(). The name of the component is followed by the function PORT MAP (). The arguments list of the function contains the name of ports in the same order as they were declared. By using this we can define the interconnection between ports.

9. It is possible to use a component twice which was declared only once.
a) True
b) False
Answer: a
Clarification: There is no restriction on the number of times a component can be used whose declaration is done. It is needed to be declared only once. Just using two or more different labels, we can use the same component again and again.

10. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations
Answer: b
Clarification: It is necessary to know the whole circuit at the component level and how these components are interconnected with each other. Since structural model describes the input and output ports of a design, so we need the components and their connections.

This set of VHDL Question Bank on “WAIT Statements – 3”.

1. Which of the following is true about WAIT UNTIL statement?
a) WAIT UNTIL statement is supported by synthesis tools
b) WAIT UNTIL statement is not supported by synthesis tools
c) WAIT UNTIL statement is supported in a clocked process only
d) WAIT UNTIL statement is supported in a combinational process

Answer: c
Clarification: Most of the synthesis tools support a single WAIT UNTIL statement in a clocked process only. That means WAIT UNTIL statement can be mostly used for implementing the sequential circuit or system.

2. Which of the following is true about WAIT ON statement?
a) WAIT ON statement is supported by synthesis tools
b) WAIT ON statement is not supported by synthesis tools
c) WAIT ON statement is supported in a clocked process only
d) WAIT ON statement is supported in a combinational process

Answer: d
Clarification: Some tools support a single WAIT ON statement as an alternative to a sensitive list in a combinational process or the process in which there is no clock signal. Therefore, WAIT ON is useful for combinational circuits.

3. In a procedure, __________ statement is not supported.
a) WAIT UNTIL
b) WAIT ON
c) WAIT FOR
d) WAIT FOR and unconditional WAIT

Answer: d
Clarification: In any procedure, the wait statements can be used (given that the procedure is not called from the process with a sensitive list). But, the WAIT FOR and simple WAIT or unconditional WAIT statement is not supported by synthesis tools inside the procedure.

5. WAIT FOR statement is useful only for _________
a) Synthesis
b) Simulation
c) Gate level implementation
d) Optimization

Answer: b
Clarification: WAIT FOR statement is only good for simulation, you can’t synthesize it. Since, synthesis means to convert the logic into actual hardware circuit. If you are using WAIT FOR 10 ns, certainly, this can’t be used in a synthesis process. So, WAIT FOR can be used for simulation only.

6. A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?
a) By using WAIT FOR statement
b) By using AFTER clause
c) By using a separate process
d) By using WAIT ON statement

Answer: c
Clarification: As we know that a process can’t contain both a sensitivity list and a WAIT statement. So, WAIT FOR can’t be used in this case. Also, AFTER clause is ignored by synthesis tool when used inside a process. So, using AFTER is also not possible. The only way to do this is using another process which can communicate with this process.

7. Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?
a) By using IF(clk = ‘1’)
b) By using ‘EVENT keyword
c) By using a CASE statement
d) By using a LOOP

Answer: b
Clarification: The clock can be detected by ‘EVENT keyword. One can use IF in conjunction with ‘EVENT to detect the clock event and high and low on the same. For example, IF(clk’EVENT AND clk = ‘1’) will detect the rising edge of the clock.

8. A wait statement can have label preceding it.
a) True
b) False

Label : WAIT {UNTIL | ON | FOR} {condition | signal | time_expression};

9. Which of the following can be used to make the process wait indefinitely?
a) WAIT FOR indefinite ns;
b) WAIT UNTIL false;
c) WAIT;
d) WAIT UNTIL true;

Answer: c
Clarification: When the WAIT is used without any clause following it then it is used as an infinite WAIT statement. The WAIT statement without any clause makes the process to wait indefinitely as there is no condition or signal or time period specified.

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Overloading”.

1. What is the meaning of overloading?
a) To use single function many times
b) To use same object for different subprograms
c) To use same name for different objects
d) To use single function many time with single call
Answer: c
Clarification: An object is said to be overloaded when the same object name exists for multiple subprograms or types. In VHDL different type of overloading is possible such as subprogram overloading, operator overloading etc.

2. Overloading a subprogram allows subprogram to ________
a) Operate on objects of different types
b) Operate on objects of same name
c) Operate on objects of different name
d) Operate on objects of same types
Answer: a
Clarification: Overloading a subprogram means to use a single name which has multiple definitions. It allows subprograms to operate on objects of different types. For example, a user define function my_func is called with two different object one of bit_vector type and another of integer type, in this case my_func must be defined twice.

3. Using overloaded subprograms and operators increase readability of code.
a) True
b) False
Answer: a
Clarification: The result of using overloaded subprograms and operators is models that are easier to read and maintain. It frees the designer from the necessity of generating countless unique names for subprograms that do virtually the same operation.

4. What is the necessary condition to overload parameters type of a subprogram?
a) The base type of two parameters must be same
b) The parameters must have a different name
c) The parameters can’t be of integer type
d) The base type of two parameters must differ
Answer: d
Clarification: To overload argument types, the base type of parameters of two functions must be different. For example, base types do not differ when two subtypes are of the same type, in that case compiler will return an error.

5. By overloading + operator, it is possible to _________
a) Use binary addition
b) Use arithmetic addition
c) Use it as subtract operator
d) Use it as ternary operator
Answer: a
Clarification: Overloading an operator allows the operator to perform the same operations on multiple types. In this case, + operator is predefined for arithmetic operation, it can be overloaded to perform the same on binary numbers.

6. Which of the following is true about the overloading of ‘+’ and ‘-‘ operators?
a) They can be defined as binary operators only
b) They can be defined as unary operators only
c) They can be defined as ternary operators only
d) They can be defined as either binary or unary operators
Answer: d
Clarification: These are the two operators which can be defined as both binary as well as unary operators. Binary operators are those which take two operands and unary operators take a single operator. It is not possible to define them as ternary operators.

7. Apart from subprogram and operator overloading, which of the following can be overloaded in VHDL?
a) Attributes
b) Types
c) IF statement
d) CASE statement
Answer: b
Clarification: Overloading of enumeration types is also possible in case of VHDL apart from operator and subprogram overloading. This means that different types can have same name just like subprogram overloading.

8. Which of the following function definition will return an error?

SUBTYPE log4 IS BIT_VECTOR (0 TO 3)
SUBTYPE log8 IS BIT_VECTOR (0 TO 7)
FUNCTION abc (a : log4) RETURN INTEGER;
FUNCTION abc (a : log8) RETURN INTEGER;

a) Only first call
b) Only second call
c) Both first and second call
d) No error
Answer: b
Clarification: Here the function abc is overloaded and both has parameters which also have same name or they are also overloaded. So, the base type of two parameters must be different. Here both have same base type which is BIT_VECTOR. Therefore, the second function will be illegal and the error is that two functions have been declared for same base type.

9. A user wants to perform a different operation on an array type and the function can be overloaded but the parameter is of same base type. How to do the same by using a single function?
a) By using conditional statement with ‘LENGTH attribute
b) By using loop statement with ‘LENGTH attribute
c) By using unconstrained array in parameters
d) It can’t be done by using single function
Answer: a
Clarification: Since the parameter is of same base type, it is just that it has different length. So, there is no need to overload the function. It can be defined in a single function only by using conditional statements. For example, one can do it like shown below:

IF(parameter’LENGTH =n) THEN 
do_this;
ELSE do_this