Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “BiCMOS Logic Gates”.

1. The BiCMOS are preferred over CMOS due to ______________
A. Switching speed is more compared to CMOS
B. Sensitivity is less with respect to the load capacitance
C. High current drive capability
D. All of the mentioned
Answer: D
Clarification: These are the 3 advantages of BiCMOS over CMOS.

2. The transistors used in BiCMOS are __________
A. BJT
B. MOSFET
C. Both BJT and MOSFETs
D. JFET
Answer: C
Clarification: BiCMOS is a combination of both MOSFET and BJT.

3. The high current driving capability of the BiCMOS is due to __________
A. NMOS in saturation mode
B. PMOS in saturation mode
C. CMOS
D. BJT
Answer: D
Clarification: BJT has the high current driving capability.

4. In BiCMOS inverter, the BJT used are __________
A. Only Npn BJT
B. Only Pnp BJT
C. Both npn and pnp BJT
D. Multi emitter npn BJT
Answer: A
Clarification: npn BJTs are used in BiCMOS inverter.

5. Which of the following is the drawback of the BiCMOS circuits?
A. Sensitivity is less load capacitance
B. Bipolar transistors are used for driving current to the load capacitance but not for the logic operations
C. Increased fabrication Complexity
D. All of the mentioned
Answer: C
Clarification: The other 2 are the merits of BiCMOS, Increased fabrication Complexity is a demerit of BiCMOS circuits.

6. The Bipolar Transistor is fabricated on __________
A. Same substrate of nMOS
B. N-well in p Substrate
C. P-well in n Substrate
D. Same substrate of pMOS
Answer: A
Clarification: BiCMOS is fabricated on the same substrate of nMOS.

7. The n-well created for Bipolar Transistor in BiCMOS is used as __________
A. Substrate
B. Collector
C. Emitter
D. None of the mentioned
Answer: B
Clarification: The created nWell is used as Collector region for BiCMOS.

8. The n-well collector is formed by __________
A. Lightly doped n-type epitaxial layer on p-Substrate
B. Heavily doped n-type epitaxial layer on p-Substrate
C. Lightly doped n-type diffused layer on p-Substrate
D. Heavily doped n-type diffused layer on p-Substrate
Answer: A
Clarification: To make the doping concentration less than the emitter.

9. The collector contact region is doped with higher concentration of n-type impurities due to __________
A. It creates a depletion region at the contact surface
B. It creates a low conductivity path between collector region and contact
C. It reduces contact resistance
D. It can withstand high voltages as compared to collector region
Answer: C
Clarification: The collector contact region is doped with higher concentration of n-type impurities reduces contact resistance.

10. Which is the proper BiCMOS inverter circuit?
A. vlsi-questions-answers-bicmos-logic-gates-q10a”>
B. vlsi-questions-answers-bicmos-logic-gates-q10b”>
C. vlsi-questions-answers-bicmos-logic-gates-q10c”>
D. vlsi-questions-answers-bicmos-logic-gates-q10d”>
Answer: C
Clarification: None.

11. In the following diagram of BiCMOS, the labels a, b, c, d denote?
vlsi-questions-answers-bicmos-logic-gates-q11″>
A. A = Collector, B = Base, C = Source, D = Drain
B. A = Emitter, B = Base, C = Drain, D = Source
C. A = Emitter, B = Collector, C = Source, D = Drain
D. A = Collector, B = Emitter, C = Drain, D = Source
Answer: C
Clarification: None.

12. What is the work of BJT in BiCMOS?
A. Current controlled Voltage source
B. Voltage controlled Current source
C. Current controlled current source
D. Voltage controlled current source
Answer: B
Clarification: The Current Ic and Ie are controlled by base emitter bias voltage.

13. In BiCMOS, the analysis of the operation of BJT is well explained by ___________
A. RC Model
B. Emitter resister model
C. Ebers Moll Model
D. Hybrid model
Answer: C
Clarification: None.

14. The Ebers Moll equivalent circuit of BJT operating in forward active region is?
A. vlsi-questions-answers-bicmos-logic-gates-q14a”>
B. vlsi-questions-answers-bicmos-logic-gates-q14b”>
C. vlsi-questions-answers-bicmos-logic-gates-q14c”>
D. None of the mentioned
Answer: B
Clarification: None.

15. The transfer characteristics of BiCMOS inverter is?
A. vlsi-questions-answers-bicmos-logic-gates-q15a”>
B. vlsi-questions-answers-bicmos-logic-gates-q15b”>
C. vlsi-questions-answers-bicmos-logic-gates-q15c”>
D. None of the mentioned
Answer: A
Clarification: None.

VLSI Interview Questions and Answers for freshers focuses on “Scaling Factors -2”.

1. Carrier density is scaled by
A. α
B. β
C. 1
D. α²
Answer: C
Clarification: Carrier density in channel Qon is scaled by 1. Carrier density is given by C0*Vgs where C0 is scaled by β and Vgs is scaled by 1/β.

2. Channel resistance Ron is scaled by
A. α
B. β
C. 1
D. α²
Answer: C
Clarification: Channel resistance Ron is scaled by 1. Channel resistance is given by (L/W)*(1/Qonµ).

3. Gate delay is given by
A. Ron/Cg
B. Ron * Cg
C. Cg/Ron
D. Cg² /Ron
Answer: B
Clarification: Gate delay Td is given as the product of Ron, channel resistance and Cg the gate capacitance.

4. Maximum operating frequency is scaled by
A. α/β
B. β/α
C. α² /β
D. β² /α
Answer: C
Clarification: Maximum operating frequency f0 is scaled by α²/β. This is given by (W/L)*(µ*C0*Vdd/Cg).

5. Saturation current is scaled by
A. α
B. β
C. 1/α
D. 1/β
Answer: D
Clarification: Saturation current Idss is scaled by 1/β. This is given by (Co*µ/2)*W/L*(Vgs-Vt)² .

6. Vgs is scaled by
A. α
B. β
C. 1/α
D. 1/β
Answer: D
Clarification: Gate to source voltage Vgs is scaled by 1/β. All voltages are scaled by 1/β.

7. Current density J is scaled by
A. α/β
B. β/α
C. α²/β
D. β²/α
Answer: C
Clarification: Current density J is scaled by α^2/β. Current density is given by Idss/A where Idss is scaled by 1/β and area A by 1/α^2.

8. Power dissipation per gate is scaled by
A. 1/α
B. 1/β
C. 1/α²
D. 1/β²
Answer: D
Clarification: Power dissipation per gate is scaled by 1/β^2. This is the sum of static component Pgs and dynamic component Pgd.

9. Power dissipation per unit area is scaled by
A. 1/α
B. 1/β
C. β²/α²
D. α²/β²
Answer: D
Clarification: Power dissipation per unit area Pa is scaled by α²/β². This is given by Pg/Ag where Pg is scaled by 1/β² and Ag by 1/α².

10. In constant voltage model, the saturation current is scaled by
A. α
B. β
C. 1
D. β²
Answer: C
Clarification: Saturation current is scaled by 1 in constant voltage model. This is because saturation current is scaled by 1/β and here in constant voltage model β is 1.

11. In constant field model, maximum operationg frequency is scaled by
A. α
B. β
C. α²
D. β²
Answer: A
Clarification: In constant field model, maximum operating frequency is scaled by α. Maximum operating frequency is scaled by α²/β and here in this model β = α.

12. In constant electric field model, power dissipation per unit area is scaled by
A. α
B. β
C. 1
D. β²
Answer: C
Clarification: Power dissipation per unit area is scaled by 1 in constant electric field model. This is scaled by α²/β² and here in constant electric field model β = α.

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VLSI Interview Questions and Answers for Experienced people focuses on “Storage Elements-2”.

1. Overhead bits are used for sensing.
A. true
B. false
Answer: A
Clarification: Overhead bits are used for sensing. Some amount of over head bits are used in one transistor dynamic memory cell.

2. Reading a cell is a _______ operation.
A. constructive
B. destructive
C. semi constructive
D. semi destructive
Answer: B
Clarification: Reading a cell is a destructive operation and the stored bit must be rewritten everytime it is read.

3. RAM is a _____ cell.
A. dynamic
B. partially dynamic
C. static
D. pseudo static
Answer: D
Clarification: RAM is a pseudo static cell. It stores data indefinitely and refreshing is not necessary.

4. Pseudo static RAM cell is built using
A. one inverter
B. two inverters
C. three inverters
D. four inverters
Answer: B
Clarification: Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.

5. Cells must be non stackable in RAM storage cell.
A. true
B. false
Answer: B
Clarification: Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when layout is made.

6. Which cell is non volatile?
A. one transistor dynamic cell
B. two transistor dymanic cell
C. four transistor dynamic cell
D. pseudo static RAM cell
Answer: D
Clarification: Pseudo static RAM cell is a non volatile cell. It is used for long time storage. Non volatile memory is also called as long term memory.

7. In RAM arrays, the transistor is of
A. minimum size
B. maximum size
C. of any size
D. size doesn’t play a role
Answer: A
Clarification: In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.

8. Which implementation is slower?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: B
Clarification: NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.

9. FOR nMOS which implementation is not suitable?
A. NAND gate
B. NOR gate
C. AND gate
D. OR gate
Answer: A
Clarification: In nMOS, NAND gate implementation is impractical because of the large number of gate requiring three or more inputs.

10. Realization of JK flipflop is based on
A. n-pass transistor
B. p-pass transistor
C. CMOS
D. BiCMOS
Answer: A
Clarification: The realization of JK flip flop is based on n-pass transistor and on inverters only.

11. Static RAM uses ____________ transistors.
A. four
B. five
C. six
D. seven
Answer: C
Clarification: Static RAM uses six transistors. In this RAM cell, read and write operations use the same port.

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VLSI Multiple Choice Questions on “Scan Design Techniques-1”.

1. The major difficulty in sequential circuit testing is in
A. determining output
B. determining internal state
C. determining external state
D. determining input combinations
Answer: B
Clarification: The major difficulty in sequential circuit testing is in determining the internal state of the circuit.

2. The design technique helps in improving
A. controllability
B. observability
C. controllability and observability
D. overall performance
Answer: C
Clarification: The design technique are directed at improving the controllability and observability of the internal states.

3. A sequential circuit contains combinational logic and storage elements in
A. feedback path
B. output node
C. input node
D. non feedback path
Answer: A
Clarification: A sequential circuit contains combinational logic and storage elements in feedback path.

4. Storage elements in scan design technique is reconfigured to form
A. RAM
B. shift registers
C. buffers
D. amplifiers
Answer: B
Clarification: Storage elements in the scan design technique is reconfigured to form a shift register known as the scan path.

5. Storage elements used are
A. D flipflops
B. JK flipflops
C. RS flipflops
D. All of the mentioned
Answer: D
Clarification: Storage elements are usually D, JK and RS flipflop elements with the classical structure being modified by the addition of a two-way multiplexer on the data inputs.

6. The sequential circuit operates in _____ mode/modes of operation.
A. only one
B. two
C. three
D. four
Answer: B
Clarification: The sequential circuit containing the scan paths has two modes of operation a normal and a test mode.

7. The efficiency of the test pattern generation is improved by
A. adding buffers
B. adding multipliers
C. partitioning
D. adding power dividers
Answer: C
Clarification: The efficiency of the test pattern generation for the overall combinational logic circuit is improved by partitioning since its depth is reduced.

8. The scan path shift register is verified by
A. shifting in all zeroes first
B. shifting in all ones first
C. adding all ones
D. adding all zeroes
Answer: B
Clarification: Before applying test patterns, the scan path shift register is verified by shifting all ones then all zeroes.

9. In level sensitive aspect, when an input change occurs, the response in
A. dependent of components
B. dependent on wiring delays
C. independent of wiring delays
D. independent of input combinations
Answer: C
Clarification: In level sensitive aspect, when an input change occurs the response is independent of the component and wiring delays within the network.

10. In test mode, storage elements are connected as
A. parallel shift registers
B. serial shift register
C. combiners
D. buffers
Answer: B
Clarification: In the test mode, storage elements are connected as a long serial shift register.

11. Which has more number of I/O pins?
A. lssd
B. partial scan
C. scan/set
D. random access scan
Answer: D
Clarification: Random access scan method’s major disadvantage is that it has more number of I/O pins and no shift registers with flipflop are used.

12. Scan/set method has no interruption to normal operation.
A. true
B. false
Answer: A
Clarification: Scan/set method has separate shift registers and has no interruption to normal operation.

13. Which method has high over head cost?
A. lssd
B. partial scan
C. scan/set
D. random access scan
Answer: C
Clarification: Scan/set method has high overhead cost in terms of additional input/output pins.

VLSI Multiple Choice Questions on “Submicron CMOS”.

1. Submicron CMOS technology is
A. faster
B. slower
C. large
D. slow and large
Answer: A
Clarification: Submicron CMOS technology is faster small and device dimensions are closely interrelated.

2. In CMOS devices, which has slower performance?
A. n-transistor
B. p-transistor
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: In CMOS devices, p-transistors have inherently slower performance than similar n-transistors and this is due to lower mobility of holes compared with that of the electrons.

3. As the channel length is scaled down, influence of mobility
A. increases
B. decreases
C. remains the same
D. does not affect
Answer: B
Clarification: As the channel lengths are scaled down, the influence of mobility starts to diminish as the effects of velocity saturation begin to be felt.

4. Current drive is ______ to mobility.
A. directly proportional
B. inversely proportional
C. logarithmically proportional
D. exponentially proportional
Answer: A
Clarification: Current drive is directly proportional to mobility and inversely proportional to the channel length L.

5. When velocity saturation occurs, Idsat is ______ to Vsat.
A. inversely proportional
B. directly proportional
C. logarithmically proportional
D. not related
Answer: B
Clarification: When velocity saturation occurs, drive current saturation Idsat is directly related to saturation velocity. It is given as Idsat = W*Cox*Vsat*(Vgs-Vt).

6. Current is dependent on ________ when saturation velocity occurs.
A. mobility
B. channel length
C. saturation velocity
D. transconductance
Answer: C
Clarification: When saturation velocity occurs, current becomes independent of mobility and the channel length and it is dependent on only saturation velocity.

7. Transconductance is independent of
A. channel width
B. channel length
C. material
D. channel depth
Answer: B
Clarification: Transconductance is a constant and it independent of the channel length. Current is independent of mobility and channel length.

8. Velocity saturation occurs at
A. lower electric field strength in n-devices
B. higher electric field strength
C. intermittent electric field strength
D. lower electric field strength in p-devices
Answer: A
Clarification: Velocity saturation occurs at lower electric field strengths in n-devices owing to their higher mobility when compared with p-devices.

9. When dimensions are scaled down ______ tends to a constant value.
A. current drive from p-transistors
B. current drive from n-transistors
C. voltage drive from p-transistors
D. voltage drive from n-transistors
Answer: B
Clarification: When dimensions are scaled down, current drive from n-transistors tends to a constant value independent of channel length.

10. At ______ length, the holes start to run into velocity saturation.
A. shorter
B. larger
C. all of the mentioned
D. none of the mentioned
Answer: A
Clarification: At shorter length, the holes start to run into velocity saturation and the current drive from p-transistors does not tend to a constant value.

11. ______ technology is used to provide for faster devices.
A. silicon based FET technology
B. silicon based MOS technology
C. gallium arsenide based MOS technology
D. gallium arsenide based VLSI technology
Answer: D
Clarification: Gallium arsenide based VLSI technology is used to provide for the faster devices which will be required as the sophistication of our system design capabilities.

12. Silicon logic is faster than gallium arsenide.
A. true
B. false
Answer: B
Clarification: Silicon logic has speed limitations that are becoming apparent in the state-of-the-art fast digital system design.

13. ________ is used with silicon to satisfy the need for very high speed integrated technology.
A. gallium oxide
B. gallium arsenide
C. silicon dioxide
D. aluminium
Answer: B
Clarification: Gallium arsenide is used in conjunction with silicon to satisfy the need for very high speed integrated technology (VHSI) in many new systems.

VLSI Multiple Choice Questions on “GaAs MESFET Logics”.

1. Normally-on logic uses
A. depletion mode MESFET
B. enhancement mode MESFET
C. depletion mode FET
D. enhancement mode FET
Answer: B
Clarification: Normally-on logic uses depletion mode MESFETs which are ON devices and when used as switching elements are required to be turned OFF.

2. Which is the approach used for normally-off logic?
A. capacitor diode FET logic
B. buffered FET logic
C. direct-coupled FET logic
D. capacitor coupled FET logic
Answer: C
Clarification: The approaches used for normally-off logic are direct-coupled FET logic, buffered DCFL and source-follower DCFL.

3. __________ is needed to facilitate turn-off.
A. positive voltage
B. power supply rail
C. ground connection
D. negative voltage
Answer: D
Clarification: Since D-MESFETs are ON devices, negative voltage is needed at the gate to facilitate turn-off.

4. __________ supply rails are required for proper operation of normally-on logic devices.
A. one
B. two
C. three
D. four
Answer: B
Clarification: Two supply rails together with level shifting networks are necessary for proper circuit operation of normally-on logic gates.

5. In direct coupled FET logic, both depletion and enhancement mode devices are used.
A. true
B. false
Answer: A
Clarification: In direct-coupled FET logic both the depletion mode and enhancement mode transistors are used. Enhancement mode FET is used as switching element and depletion mode FET is used as load.

6. DCFL circuits have
A. large voltage swing
B. small voltage swing
C. large noise margins
D. more complexity
Answer: B
Clarification: In direct-coupled FET logic, only small voltage swings are possible and also relatively small noise margins.

7. Which circuits have weak load drive capability?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: A
Clarification: DCFL circuits have weak load drive capability. This can be improved by the introduction of super buffers with expense of extra area.

8. Which logic is suitable for large loads?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: B
Clarification: DCFL with super buffers are used for larger loads to be driven whereas DCFL circuits are used for light load conditions.

9. Which circuit has large noise margin?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: D
Clarification: Source follower DCFL FET logic has power dissipation and also switching delay. This has a larger noise margin which is due to pull-up transistor being able to be turned off.

10. Which logic is suitable for And-OR-Invert function?
A. DCFL
B. DCFL with super buffers
C. FET logic
D. SDCFL
Answer: D
Clarification: The source-follower DCFL FET logic is most suitable for realization of And-OR-Invert function which usually assists in the optimization of logical functions.