Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “Inverter Delays”.

1. The resistance value associated with Rp.u is?
A. 2Rs
B. Rs
C. 4Rs
D. Rs/2
Answer: C
Clarification: The resistance value associated with Rp.u. is 4Rs. Resistance is the measure of difficulty to pass an electric current through that material.

2. The resistance value associated with Rp.d. is?
A. 2Rs
B. Rs
C. 4Rs
D. Rs/2
Answer: B
Clarification: The resistance value associated with Rp.d. is 1Rs. This is the measure of difficulty to pass current through the pull-down device.

3. The overall delay of nMOS inverter pair is?
A. 4Ʈ
B. Ʈ
C. 5Ʈ
D. 2Ʈ
Answer: C
Clarification: The overall delay of nMOS inverter pair is Ʈ+4Ʈ = 5Ʈ. This delay is the time taken for the input signal to get inverted and arrive at the output.

4. The inverter pair delay for inverters having 4:1 ratio is?
A. 4Ʈ
B. Ʈ
C. 5Ʈ
D. 2Ʈ
Answer: C
Clarification: The inverter pair delay for inverters having 4:1 ratio is 5Ʈ. This measure of delay is for two inverters, in which the output of the first is given as the input for the second inverter.

5. The asymmetry of resistance value can be eliminated by ____________
A. decreasing the width
B. increasing the width
C. increasing the length
D. increasing the width
Answer: B
Clarification: The asymmetry of resistance value can be eliminated by increasing the width of the p-device channel.

6. The ratio of rise time to fall time can be equated to ___________
A. βn/βp
B. βp/βn
C. βp*βn
D. βp/2βn
Answer: A
Clarification: The ratio of rise time to fall time can be equated to βn/βp. Rise time is the time taken by a signal to change from a specified low value to a specified high value. Fall time is the time taken for the amplitude of a pulse to decrease from a specified value to another specified value.

7. The value µn is equal to ___________
A. µp
B. 0.5µp
C. 1.5µp
D. 2.5µp
Answer: D
Clarification: The value of µn = 2.5 µp. This shows that µn value is greater than that of the µp.

8. Which quantity is slower?
A. rise time
B. fall time
C. all of the mentioned
D. none of the mentioned
Answer: A
Clarification: Rise time is slower by a factor of 2.5 than fall time.

9. Condition for achieving symmetrical operation is ___________
A. Wp = Wn
B. Wp greater than Wn
C. Wp lesser than Wn
D. Wp lesser than 2Wn
Answer: B
Clarification: The condition for achieving symmetrical operation is Wp = 2.5 Wn.

10. Rise time and fall time is _____ to load capacitance CL.
A. directly proportional
B. inversely proportional
C. exponentially equal
D. not related
Answer: A
Clarification: Rise time and fall time is directly proportional to load capacitance CL.

11. Rise time and fall time is ________ to Vdd.
A. directly proportional
B. inversely proportional
C. exponentially equal
D. not related
Answer: B
Clarification: Rise time and fall time are inversely proportional to Vdd. This shows that if Vdd is reduced fall time and rise time increase.

VLSI Multiple Choice Questions on “Gate Logic”.

1. Gate logic is also called as
A. transistor logic
B. switch logic
C. complementary logic
D. restoring logic
Answer: D
Clarification: Gate logic is also called as restoring logic. This is a logic circuitry designed so that even with an imperfect input pulse a standard output occurs at the exit of each successive logic gate.

2. Both NAND and NOR gates can be used in gate logic.
A. true
B. false
Answer: A
Clarification: Both NAND and NOR gates can be used in gate logic along with CMOS and AND and OR logic can be used in switch logic.

3. The CMOS inverter has _____ power dissipation.
A. low
B. more
C. no
D. very less
Answer: C
Clarification: The CMOS inverter has no static current and no power dissipation. Static charge remains until it is able to move away by means of electric discharge.

4. As the number of inputs increases, the NAND gate delay
A. increases
B. decreases
C. does not vary
D. exponentially decreases
Answer: A
Clarification: As the number of inputs increases, the NAND gate delay also increases because computation considering or using each input additional time is needed.

5. NAND gate delay can be given as
A. Ʈint
B. Ʈint/n
C. n*Ʈint
D. 2n*Ʈint
Answer: C
Clarification: NAND gate delay can be given as the product of number of inputs n and the nMOS inverter delay Ʈint.

6. In CMOS NAND gate, p transistors are connected in
A. series
B. parallel
C. cascade
D. random
Answer: B
Clarification: In CMOS NAND gate, p transistors are connected in parallel but once again the geometries may require thought when several inputs are required.

7. BiCMOS is used for ____ fan-out.
A. less
B. more
C. no
D. very less
Answer: B
Clarification: BiCMOS NAND can be used when large fan-out is necessary. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.

8. Which can handle high capacitance load?
A. NAND
B. nMOS NAND
C. CMOS NAND
D. BiCMOS NAND
Answer: D
Clarification: BiCMOS NAND can handle high capacitance load. It is more complex and it can handle high capacitance load such as in the I/O region of a chip.

9. Which gate is faster?
A. AND
B. NAND
C. NOR
D. OR
Answer: C
Clarification: NOR gate is faster. NAND is more complex than NOR and thus NOR is faster and efficient.

10. For a pseudo nMOS design the impedance of pull up and pull down ratio is
A. 4:1
B. 1:4
C. 3:1
D. 1:3
Answer: C
Clarification: For a pseudo nMOS design, the ratio of Zp.u. and Zp.d. is 3:1.

VLSI Multiple Choice Questions on “System Delays”.

1. Which provides large capacitance?
A. load capacitance
B. bus wiring capacitance
C. sheet capacitance
D. area capacitance
Answer: B
Clarification: Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.

2. Bus wiring capacitance is driven through
A. one transistor
B. two transistors
C. three transistors
D. no transistors
Answer: A
Clarification: Bus wiring capacitance is driven through pull-up and pull-down transistors and through atleast one pass transistor or transmission gate in the series.

3. What is the delay of input pads?
A. 5Ʈ
B. 10Ʈ
C. 40Ʈ
D. 30Ʈ
Answer: D
Clarification: Input pad always contains over voltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ʈ.

4. The total delay for the select register circuit is
A. 33Ʈ
B. 60Ʈ
C. 55Ʈ
D. 73Ʈ
Answer: D
Clarification: The total delay for the select register is 73Ʈ. It is the sum of delays of input pad, three pass transistors and driver inverter pair.

5. Delay for data propagation is
A. 10 nsec
B. 50 nsec
C. 100 nsec
D. 150 nsec
Answer: C
Clarification: Data is propagated through bus. Bus can be bidirectional but at data can be propagated through bus only at one direction at a time. The delay for this data propagation is 100nsec.

6. Which is the longest delay in adder process?
A. sum delay
B. carry delay
C. propagation delay
D. inverter delay
Answer: B
Clarification: The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.

7. The total delay for the adder process is
A. 100 nsec
B. 200 nsec
C. 220 nsec
D. 250 nsec
Answer: C
Clarification: The total delay for the adder process is 220 nsec. The total delay is the sum of select register delay, bus delays and carry chain delays.

8. The refreshing clock period should propagate through
A. memory cell
B. wiring
C. carry chain
D. any sub unit
Answer: B
Clarification: The clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.

9. The value of Ʈ for 5 micron technology is always constant.
A. true
B. false
Answer: B
Clarification: The range of value of Ʈ for 5 micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.

10. The total clock period for adder process is
A. 100 nsec
B. 150 nsec
C. 200 nsec
D. 250 nsec
Answer: D
Clarification: The total clock period of the adder process is 250 nsec which is the sum of all the delay (220 nseC. and the period of different phases of the process.

VLSI online test focuses on “LFSR-2”.

1. Primitive polynomial should have a minimum number of zero coefficient.
A. true
B. false
Answer: A
Clarification: Primitive polynomials with a minimum number of zero coefficients are the desired characteristic polynomial for the LFSR.

2. The minimum number of EX-OR gates used is in between
A. 0 to 2
B. 1 to 3
C. 2 to 5
D. 3 to 7
Answer: B
Clarification: The minimum number of EX-OR gates used for the linear feedback shift register is in between 1 and 3.

3. The LFSR takes reasonable time if the n value is
A. below 50
B. below 100
C. below 10
D. below 25
Answer: D
Clarification: The LFSR’s degree value is limited to 22 to 25 for producing maximal length sequence in reasonable amount of time.

4. Which is used to initialize the LFSRs?
A. zeroes
B. ones
C. preset of flip-flop
D. EX-OR gate
Answer: C
Clarification: The preset of each flip-flop in LFSR to used to initialize the LFSRs and initial non-zero coefficient or state ensures maximal length sequence is obtained.

5. The beginning and end of the maximal length sequence can be determined using
A. AND gate
B. NAND gate
C. AND or NAND gate
D. Both AND and NAND gate
Answer: C
Clarification: The beginning and end of the maximal length sequence of the LFSR can be determined using AND gate or NAND gate.

6. Preloading different starting value for the LFSR is called as
A. seeding
B. reseeding
C. deseeding
D. pre-seeding
Answer: B
Clarification: Initializing with a specific value to the LFSR is called as seeding and preloading different starting value is called as reseeding.

7. The primitive polynomial has a property according to which the runs of 1s ______ to runs of 0s.
A. equal
B. greater
C. lesser
D. not related
Answer: A
Clarification: The primitive polynomial has a property of randomness according to which the runs of 1s equal to runs of 0s.

8. The total number of runs is given mathematically as
A. 2ⁿ
B. 2^(n-1)
C. 2⁽ⁿ⁺¹⁾
D. 2ⁿ-1
Answer: B
Clarification: The total number of runs is given as 2^(n-1) which is the total number of transitions from 1 to 0 or from 0 to 1.

9. ______ of the runs will have a length of 1.
A. one third
B. one fourth
C. half
D. one eight
Answer: C
Clarification: The length of the runs are distributed as – half of the runs have length 1, quarter with length 2, a eight length 3 and a sixteenth length 4 and so on.

10. The length of the runs is dependent on whether the LFSR is internal or external feedback.
A. true
B. false
Answer: B
Clarification: The length of the run is independent of whether the LFSR is internal or external feedback and LFSR is also known as pseudo random pattern generator.

11. Which process is used to develop the LFSR method?
A. random method
B. gaussian method
C. deterministic method
D. bernoulli method
Answer: D
Clarification: Bernoulli method is used in modelling the linear feedback shift register testing method and this is called as random pattern generation method.

all areas of VLSI for online tests,

VLSI Multiple Choice Questions on “MESFET”.

1. The gallium arsenide field effect transistor is ________ majority carrier device.
A. bulk current insulation
B. bulk current conduction
C. bulk voltage insulation
D. bulk voltage conduction
Answer: B
Clarification: The gallium arsenide field effect transistor is a bulk current-conduction majority carrier device and is fabricated from bulk gallium arsenide.

2. Method used for fabrication of GaAs FET is
A. ion implantation
B. disposition
C. diffusion
D. conduction
Answer: A
Clarification: The methods used for fabrication of gallium arsenide field effect transistors are high-resolution photolithography and ion implantation.

3. How many masking stages does fabrication of GaAs FET require?
A. five
B. four
C. ten
D. eight
Answer: D
Clarification: The fabrication of GaAs field effect transistor requires six to eight masking stages and processing is relatively simple.

4. Which region is heavily doped?
A. drain
B. gate
C. n-region
D. p-region
Answer: A
Clarification: In GaAs FET, a narrow metal Schottky barrier gate separates the more heavily doped drain and source.

5. Which MOSFET contains Schottky diode?
A. GaAs
B. Ga
C. Si
D. SiO2
Answer: A
Clarification: GaAs MOSFET differs from silicon MOSFET due to the presence of Schottky diode to separate two thin n-type regions.

6. D type and E type MESFETs operates by ________ of existing doped channel.
A. depletion
B. enhancement
C. e type MESFET
D. d type MESFET
Answer: A
Clarification: D type and E type MESFETs, that is ON and OFF devices operates by the depletion of an existing doped channel.

7. Which is ON device?
A. e type MESFET
B. d type MESFET
C. depletion
D. enhancement
Answer: B
Clarification: D-MESFET is normally ‘ON’ and its threshold voltage is negative and E-MESFET is ‘OFF’ and its threshold voltage is positive.

8. The threshold voltage cannot be determined using
A. concentration density
B. channel thickness
C. implanted impurity
D. channel depth
Answer: D
Clarification: The threshold voltage can be determined using concentration density, channel thickness and implanted impurity but cannot be determined using channel depth.

9. A highly doped thick channel exhibits _______ threshold voltage.
A. smaller negative
B. smaller positive
C. larger negative
D. larger positive
Answer: C
Clarification: A highly doped thick channel exhibits a large negative threshold voltage. By reducing channel thickness and concentration density, positive threshold in E-MESFET can be fabricated.

10. The MESFET has maximum
A. gate to drain voltage
B. gate to source voltage
C. source voltage
D. drain voltage
Answer: B
Clarification: The MESFET has a maximum gate to source voltage Vgs of about 0.7-0.8 volt owing to the diode action of schottky diode gate.

11. Schottky barrier is created due to the difference in
A. voltages
B. thickness
C. work function
D. density
Answer: C
Clarification: Schottky barrier is an electrostatic potential barrier created at the interface as a result of the difference in work function of the two materials.

12. As the separation between metal-semiconductor surface is reduced, induction charge
A. increases
B. decreases
C. remains constant
D. is not affected
Answer: A
Clarification: As the separation between metal-semiconductor surface is reduced, induction charge in the semiconductor increases and also the space charge layer widens.

13. In MESFET for gate _____ junction is used.
A. pnp junction
B. npn junction
C. schottky junction
D. n junction
Answer: C
Clarification: Metal semiconductor field effect transistor is similar to JFET. In this instead of using pn junction for gate, Schottky gate is used.

14. MESFET is constructed in
A. SiC
B. InP
C. GaAs
D. All of the mentioned
Answer: D
Clarification: MESFET is constructed in compound semiconductor technologies lacking high quality surface such as GaAs, InP and SiC.

VLSI Multiple Choice Questions on “Noise Margin”.

1. Noise Margin is:
A. Amount of noise the logic circuit can withstand
B. Difference between VOH and VIH
C. Difference between VIL and VOL
D. All of the Mentioned
Answer: D
Clarification: Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by the difference between VOH and VIH or VIL and VOL.

2. The VIL is found from transfer characteristic of inverter by:
A. The point where the straight line at VOH ends
B. The slope of the transition at a point at which the slope is equal to -1
C. The midpoint of the transition line
D. All of the mentioned
Answer: B
Clarification: The VIL is the input voltage at which the slope of the transition will be equal to -1.

3. The VIH is found from transfer characteristic of inverter by:
A. The point where straight line at VOH ends
B. The slope of the transition at a point at which the slope is equal to -1
C. The midpoint of the transition line
D. All of the mentioned
Answer: B
Clarification: The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points we will find the slope to be -1.

4. The relation between threshold voltage and Noise Margin is:
A. Vth = sqrt(Noise Margin)
B. Vth = NMH – NML
C. Vth = (NMH+NML)/2
D. None of the metioned
Answer: D
Clarification: None.

5. The Lower Noise Margin is given by:
A. VOL – VIL
B. VIL – VOL
C. VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
D. All of the Mentioned
Answer: B
Clarification: Noise margin = VIL-VOL.

6. The Higher Noise Margin is given by:
A. VOH – VIH
B. VIH – VOH
C. VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
D. All of the mentioned
Answer: A
Clarification: Noise margin = VOH – VIH.

7. The Uncertain or transition region is between:
A. VIH and VOH
B. VIL and VOL
C. VIH and VIL
D. VOH and VOL
Answer: C
Clarification: In Input the uncertain region is VIH and VIL.

8. The noise immunity ____________ with noise margin.
A. Decreases
B. Increases
C. Constant
D. None of the Mentioned
Answer: B
Clarification: The noise immunity is directly proportional to noise margin.

9. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
Answer: C
Clarification: Logic output 0 from first gate is considered as logic input 0 at second gate as it lies within the range.

10. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
Answer: B
Clarification: The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.

11. Input Voltage between VIL and VOL is considered as:
A. Logic Input 1
B. Logic Input 0
C. Uncertain
D. None of the mentioned
Answer: B
Clarification: None.

12. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as:
A. Logic input 1
B. Uncertain
C. Logic input 0
D. None of the mentioned
Answer: B
Clarification: The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.

13. Determine the Noise Margin for 5V TTL inverter gate:
vlsi-questions-answers-noise-margin-q13″>
A. NMH = 0.4V and NML =0.4V
B. NMH = 2.4V and NML = 0.4V
C. NMH = 2V and NML = 0.8V
D. NMH = 1.5V and NML = 0.4V
Answer: A
Clarification: None.

14. Determine the Noise Margin for 5V CMOS inverter gate:
vlsi-questions-answers-noise-margin-q14″>
A. NMH = 1V and NML = 1V
B. NMH = 3.7V and NML = 0.2V
C. NMH = 0.9V and NML = 1V
D. NMH = 0.2V and NML = 0.5V
Answer: C
Clarification: None.

15. Noise margin of CMOS is:
A. Better than TTL and ECL
B. Less than TTL and ECL
C. Equal to TTL and ECL
D. None of the Mentioned
Answer: A
Clarification: None.