Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “BiCMOS Technology”.

1. MOS technology has more load driving capability.
A. true
B. false
Answer: B
Clarification: One of the disadvantages of MOS technology is it has limited load driving capabilities.

2. What is the disadvantage of the MOS device?
A. limited current sourcing
B. limited voltage sinking
C. limited voltage sourcing
D. unlimited current sinking
Answer: A
Clarification: MOS devices have limited current sourcing and current sinking abilities.

3. What are the advantages of BiCMOS?
A. higher gain
B. high frequency characteristics
C. better noise characteristics
D. all of the mentioned
Answer: D
Clarification: BiCMOS provides higher gain, better noise and high frequency characteristics than MOS transistors.

4. What are the features of BiCMOS?
A. low input impedance
B. high packing density
C. high input impedance
D. bidirectional
Answer: A
Clarification: Some of the features of BiCMOS are low input impedance, low packing density, unidirectional, high output drive current, etc.

5. BiCMOS has low power dissipation.
A. true
B. false
Answer: B
Clarification: BiCMOS has high power dissipation and CMOS has low power dissipation.

6. CMOS is __________
A. unidirectional
B. bidirectional
C. directional
D. none of the mentioned
Answer: A
Clarification: BiCMOS is unidirectional and CMOS is bidirectional.

7. In bipolar transistor, its quality can be improved by __________
A. increasing collector resistance
B. decreasing collector resistance
C. collector resistance does not affect the quality
D. decreasing gate resistance
Answer: B
Clarification: The quality of bipolar transistor can be improved by reducing the collector resistance, which can be done by using the additional layer of n+ subcollector.

8. BiCMOS can be used in __________
A. amplifyig circuit
B. driver circuits
C. divider circuit
D. multiplier circuit
Answer: B
Clarification: BiCMOS is more advantageous and improved than CMOS and it can be used in I/O and driver circuits.

9. What are the advantages of E-beam masks?
A. small feature size
B. larger feature size
C. looser layer
D. complex design
Answer: A
Clarification: The advantages of E-beam masks are it has tighter layer to layer registration and it has smaller feature sizes.

10. Which process is used in E-beam machines?
A. raster scanning
B. vector scanning
C. raster & vector scanning
D. none of the mentioned
Answer: C
Clarification: The two approaches to the design of E-beam machines are raster scanning and vector scanning.

11. What is the feature of vector scanning?
A. faster
B. slow
C. easy handling
D. very simple design
Answer: A
Clarification: Vector scanning is faster but data handling involved is more complex. Vector scanning is done between the end points.

12. Which has high input resistance?
A. nMOS
B. CMOS
C. pMOS
D. BiCMOS
Answer: B
Clarification: CMOS technology has high input resistance and is best for constructing simple low-power logic gates.

13. BiCMOS has lower standby leakage current.
A. true
B. false
Answer: B
Clarification: BiCMOS has the potential for high standby leakage current and has high power consumption compared to CMOS.

VLSI Multiple Choice Questions on “Drivers”.

1. For shorter delays ______ resistance should be used.
A. smaller
B. larger
C. does not depend on resistance
D. very large
Answer: A
Clarification: For shorter delays low resistance should be used as delay is directly proportional or related to resistance.

2. To reduce resistance value of inverters, channels must be made __________
A. wider
B. narrower
C. lenghthier
D. shorter
Answer: A
Clarification: Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. imply low L:W ratios and thus consequently an inverter to meet this need occupies a larger area.

3. As width increases, capacitive load __________
A. increases
B. decreases
C. does not change
D. exponentially increases
Answer: A
Clarification: As width of the channel increases, capacitive load also increases and with this the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.

4. Delay per stage for logic 0 to 1 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: A
Clarification: Delay per stage for logic 0 to 1 transition can be given as fƮ. With large f, N decreases but delay per stage increases.

5. Delay per stage for logic 1 to 0 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: D
Clarification: Delay per stage for logic 1 to 0 transition can be given as 4fƮ. Using the delay for transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.

6. What is the total delay of an nMOS pair?
A. fƮ
B. 2fƮ
C. 5fƮ
D. 4fƮ
Answer: C
Clarification: Total delay of an nMOS pair is equal to 5fƮ. This can be calculated by knowing delay per stage, that is for two different transitions from 0 to 1 and vice versa.

7. What is the total delay of a CMOS pair?
A. 5fƮ
B. 7fƮ
C. 8fƮ
D. 4fƮ
Answer: B
Clarification: Total delay of an CMOS pair is equal to 7fƮ. This can be calculated by knowing thee delay per stage of CMOS.

8. The number of stages N can be given as ___________
A. ln(y)*ln(f)
B. ln(y)/ln(f)
C. ln(f)/ln(y)
D. ln(f)/ln(2y)
Answer: B
Clarification: The number of stages N can be given as ln(y)/ln(f). By knowing whether the number of stages N is even or odd we can calculate the total delay for nMOS, CMOS etc.

9. When number of stages N is even, the total delay for nMOS can be?
A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer: B
Clarification: When number of stages N is even, the total delay for nMOS can be given as 2.5NfƮ. This is calculated by using the formula (N/2)*5fƮ.

10. When number of stages N is even, the total delay for CMOS can be?
A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer: C
Clarification: When the number of stages N is even, the total delay for CMOS can be given as 3.5NfƮ. This is calculated by using the formula (N/2)*7fƮ.

11. In BiCMOS drivers, the input voltage Vbe is _______ on base width.
A. directly proportional
B. inversely proportional
C. logarithmically proportional
D. exponentially proportional
Answer: C
Clarification: In BiCMOS driver, the input voltage Vbe is logarithmically proportional to the base width Wb and on electron mobility.

12. Which has a larger value?
A. Tin
B. TL
C. Rc
D. None of the mentioned
Answer: A
Clarification: In BiCMOS drivers, the initial time Tin necessary to charge base emitter junction is larger than the time TL requires to charge the output load capacitance.

13. In BiCMOS driver, a good bipolar transistor should have ___________
A. low Rc
B. high hfe
C. high gm
D. all of the mentioned
Answer: D
Clarification: In BiCMOS drivers, a good bipolar transistor should have low Rc, high hfe, high gm, etc.

VLSI Multiple Choice Questions on “CMOS Logics”.

1. In Pseudo-nMOS logic, n transistor operates in
A. cut off region
B. saturation region
C. resistive region
D. non saturation region
Answer: B
Clarification: In Pseudo-nMOS logic, n transistor operates in a saturation region and p transistor operates in resistive region.

2. The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device.
A. 50%
B. 30%
C. 60%
D. 70%
Answer: C
Clarification: The power dissipation in Pseudo-nMOS is reduced to about 60% compared to nMOS device.

3. Pseudo-nMOS has higher pull-up resistance than nMOS device.
A. true
B. false
Answer: A
Clarification: Pseudo-nMOS has higher pull-up resistance than nMOS device and thus inverter pair delay is larger.

4. In dynamic CMOS logic _____ is used.
A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer: D
Clarification: In dynamic CMOS logic, four phase clock is used in which actual signals are used to derive the clocks.

5. In clocked CMOS logic, output in evaluated in
A. on period
B. off period
C. both periods
D. half of on period
Answer: A
Clarification: In clocked CMOS logic, the logic is evaluated only in the on period of the clock. And owing to the extra transistor in series, slower rise time and fall times are expected.

6. In clocked CMOS logic, rise time and fall time are
A. faster
B. slower
C. faster first and then slows down
D. slower first and then speeds up
Answer: B
Clarification: In clocked CMOS logic, rise time and fall time are slower because of more number of transistors in series.

7. In CMOS domino logic _____ is used.
A. two phase clock
B. three phase clock
C. one phase clock
D. four phase clock
Answer: C
Clarification: In CMOS domino logic, single phase clock is used. Clock signals distributed on one wire is called as single or one phase clock.

8. CMOS domino logic is same as ______ with inverter at the output line.
A. clocked CMOS logic
B. dynamic CMOS logic
C. gate logic
D. switch logic
Answer: B
Clarification: CMOS domino logic is same as that of the dynamic CMOS logic with inverter at the output line.

9. CMOS domino logic occupies
A. smaller area
B. larger area
C. smaller & larger area
D. none of the mentioned
Answer: A
Clarification: CMOS domino logic structure occupies smaller area than conventional CMOS logic as only n-block is used.

10. CMOS domino logic has
A. smaller parasitic capacitance
B. larger parasitic capacitance
C. low operating speed
D. very large parasitic capacitance
Answer: A
Clarification: CMOS domino logic has smaller parasitic capacitance and higher operating speed.

11. In CMOS domino logic _______ is possible.
A. inverting structure
B. non inverting structure
C. inverting and non inverting structure
D. very complex design
Answer: B
Clarification: In CMOS domino logic, only non inverting structures are possible because of the presence of the inverting buffer.

12. CMOS domino logic can be expressed diagramatically as
A. vlsi-questions-answers-cmos-logics-q12a”>
B. vlsi-questions-answers-cmos-logics-q12b”>
C. vlsi-questions-answers-cmos-logics-q12c”>
D.vlsi-questions-answers-cmos-logics-q12d”>
Answer: A
Clarification: The correct form of CMOS domino logic representation is as given in the answer.

VLSI Multiple Choice Questions on “Design Styles”.

1. In which design all circuitry and all interconnections are designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: A
Clarification: Full custom design is the complete design for the implementation. It contains all circuitry and all interconnections/communication paths.

2. Which design contains only the interconnections designed?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Clarification: Gate array design which is also known as uncommitted logic array design has the design of only the interconnections/communication paths.

3. In which method regularity is used to reduce complexity?
A. random approach
B. hierarchical approach
C. algorithmic approach
D. semi-design approach
Answer: B
Clarification: Hierarchical approach is in the one in which principles of iteration or regularity can be used to reduce the complexity of the design task.

4. Size of the die is determined using
A. transistor size
B. inverter size
C. area of the circuitry
D. length of the circuitry
Answer: C
Clarification: Size of the die is determined by the area occupied by the circuitry. Large die sizes area associated with poor yields and high costs.

5. Which design is faster?
A. full custom design
B. semi-custom design
C. gate array design
D. transistor design
Answer: C
Clarification: Gate array design is faster than a prototype full-custom design and the final custom designs must be carefully optimized.

6. Which has relatively low-level capabilities?
A. hand-crafted designs
B. computer assisted textual entry
C. computer assisted graphical entry
D. silicon compiler-based design
Answer: B
Clarification: Computer-assisted textual entry has programs which may be relatively low-level capabilities and it allows the entry of rectangular boxes, wires, etc.

7. Computer-assisted graphical entry is done through
A. monochrome
B. grayscale graphics
C. bichrome
D. trichrome
Answer: A
Clarification: Computer-assisted graphical entry of mask geometry is through either monochrome or color graphics terminal.

8. Which method is used for verification along with generation?
A. hand-crafted designs
B. computer assisted textual entry
C. computer assisted graphical entry
D. silicon compiler-based design
Answer: C
Clarification: Computer-assisted graphical entry method encourages regularity and are generally used with a generate then verify design philosophy.

9. Which method uses high level programming language?
A. hand-crafted designs
B. computer assisted textual entry
C. computer assisted graphical entry
D. silicon compiler-based design
Answer: D
Clarification: Silicon compiler-based design uses high level approach and uses special languages like high level language compilers.

10. The set of design rules does not give
A. widths
B. spacing
C. colors
D. overlaps
Answer: C
Clarification: Communication between the fabrication house and the designer takes the form of a set of design rules with gives clearance, widths, spacing, overlaps, etc.

VLSI Multiple Choice Questions on “Cellular Automata”.

1. Cellular automata produce
A. exhaustive patterns
B. exhaustive pseudo random patterns
C. random patterns
D. pseudo random patterns
Answer: D
Clarification: Cellular automata is similar to linear feedback shift register and it generates pseudo-random patterns.

2. In which method the effect of bit shifting is not observed or visible?
A. internal feedback LFSR
B. external feedback LFSR
C. cellular automata
D. counters
Answer: C
Clarification: The effect of bit shifting is not observed in cellular automata as it is done in linear feedback shift register.

3. The patterns produced using ______ is less random.
A. LFSR
B. Cellular automata
C. NAND gates
D. Shift registers
Answer: A
Clarification: The patterns produced by cellular automata is more random in nature than those produced using LFSR.

4. Which method needs more number of EX-OR gates?
A. internal feedback LFSR
B. counters
C. external feedback LFSR
D. cellular automata
Answer: D
Clarification: The construction of cellular automata is not as simple as LFSR and thus cellular automata needs more number of EX-OR gates.

5. The construction of CA register is based on
A. logical relationship of flip-flop
B. EX-OR gate
C. primitive polynomial
D. degree of the polynomial
Answer: A
Clarification: The construction of cellular automata is based on the logical relationship of each flip-flop to its two neighbours.

6. The next state for rule 150 is obtained by
A. x(t)
B. x(t+1)+x(t)+x(t-1)
C. x(t+1)+x(t-1)
D. x(t)+x(t-1)
Answer: B
Clarification: The next state for rule 150 is obtained by exploring three current state values – itself, previous flip-flop and next flip-flop.

7. The next state for rule 90 is obtained by
A. x(t)
B. x(t+1)+x(t)+x(t-1)
C. x(t+1)+x(t-1)
D. x(t)+x(t-1)
Answer: C
Clarification: The next state for rule 90 is obtained by exploring two current values – the state value of previous and the next flip-flop.

8. Which occupies lesser area?
A. internal feedback LFSR
B. external feedback LFSR
C. null condition CA
D. cyclic boundary CA
Answer: D
Clarification: The area occupied by null boundary cellular automata is comparatively lesser than that used by cyclic boundary CA.

9. The maximal length sequence is given by
A. 2ⁿ
B. 2ⁿ + 1
C. 2ⁿ – 1
D. 2n
Answer: C
Clarification: The maximal length sequence is given by 2ⁿ – 1 in null condition boundary cellular automata.

10. Rule 90 CA minimizes area when compared to rule 150.
A. true
B. false
Answer: A
Clarification: Maximizing the use of rule 90 cellular automata minimizes area overhead when compared to using rule 150 cellular automata.

VLSI Multiple Choice Questions on “GaAs Fabrication -1”.

1. Gallium arsenide crystals are grown from
A. boron oxide
B. silicon oxide
C. silicon nitride
D. boron nitride
Answer: D
Clarification: Growth of gallium arsenide crystals from high purity boron nitride cubicles is becoming the primary growth technique.

2. Wafers in GaAs fabrication are thermally unstable.
A. true
B. false
Answer: B
Clarification: The fabrication of GaAs includes production of round wafers and they are thermally stable and have superior semi-insulating properties.

3. The sequence of the steps followed in fabrication of GaAs is

i. lapping
ii. polishing
iii. grinding
iv. wafer scrubbing

A. ii, iii, i, iv
B. i, ii, iii, iv
C. iii, i, ii, iv
D. iv, i, ii, iii
Answer: C
Clarification: The steps followed in fabrication of GaAs are grinding the As-grown boules, wafering, edge rounding, lapping, polishing and then wafer scrubbing.

4. Which devices are fabricated using planar process?
A. enhancement mode MESFET
B. depletion mode MESFET
C. enhancement mode MOSFET
D. depletion mode MOSFET
Answer: B
Clarification: The depletion mode devices are fabricated using planar process where n-type dopants are directly implanted into semi-insulating GaAs.

5. Threshold voltage can be varied by
A. varying impurity concentration
B. varying doping level
C. varying channel length
D. varying source voltage
Answer: B
Clarification: Threshold voltage in GaAs can be varied by varying the channel thickness and the doping level of the active region.

6. Stable native oxide was produced by
A. oxidation of silicon
B. oxidation of gallium
C. oxidation of boron
D. oxidation of aluminium
Answer: A
Clarification: The driving force with siicon technology were brought about as the result of presence of stable native oxide which was readily produceded through oxidation of silicon.

7. In GaAs technology, deposited dielectric films brings about
A. passivation
B. combination
C. decomposition
D. diffusion
Answer: A
Clarification: In GaAs technology, due to the absence of a stable native oxide deposited dielectric films brings about passivation or encapsulation.

8. Formation of n-active layer is achieved by
A. indirent ion implantation
B. direct ion implantation
C. liquifying
D. wafering
Answer: B
Clarification: Formation of n-active layer is achieved by direct ion implantation into the GaAs semi-insulating substrate through the insulating layer.

9. Implantation of ________ is done for the formation of source and drain.
A. n- layer
B. n+ layer
C. p- layer
D. p+ layer
Answer: B
Clarification: Implantation of a deep low resistivity n+ layer is done for the formation of source and drain and n-layer for the formation of channel layer.

10. The channel resistance is high for
A. source contact
B. drain contact
C. gate contact
D. source and drain contacts
Answer: D
Clarification: The channel resistance is in the order of 1000 to 2500 ohm/square which is too high for source and drain contacts.

11. Stress at the interface cannot arise from
A. lattice mismatch
B. intrinsic stress
C. thermal mismatch
D. pressure mismatch
Answer: D
Clarification: Mechanical stability of thin film encapsulation layer depends upon stress at the interface and this can originate from lattice mismatch, intrinsic stress and thermal mismatch.

12. Which has the greatest mismatch?
A. Si
B. Ga
C. GaAs
D. SiO₂
Answer: D
Clarification: SiO₂ has the greatest mismatch and its cofficient of thermal expansion is 0.5×10^-6/degree celsius.

13. Which was employed as the first level capping material?
A. SiO₂
B. SiO
C. Si3N4
D. Si2N4
Answer: A
Clarification: Si3N4 has a dielectric constant of 7 compared to 3.9 for silicondioxide and silicondioxide was initially employed as the first-level capping material.