Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “Ids versus Vds Relationships”.

1. Ids depends on ___________
A. Vg
B. Vds
C. Vdd
D. Vss
Answer: B
Clarification: Ids depends on both Vgs and Vds. The charge induced is dependent on the gate to source voltage Vgs also charge can be moved from source to drain under influence of electric field created by Vds.

2. Ids can be given by __________
A. Qc x Ʈ
B. Qc / Ʈ
C. Ʈ / Qc
D. Qc / 2Ʈ
Answer: B
Clarification: Ids can be given as charge induced in the channel(QC. divided by transit time (Ʈ). Ids is equivalent to (-IsD..

3. Transit time can be given by __________
A. L / v
B. v / L
C. v x L
D. v x d
Answer: A
Clarification: Transit time (Ʈ) can be given by lenght of channel(L) by velocity(v). Transit time is the time required for an electron to travel between two electrodes.

4. Velocity can be given as __________
A. µ / Vds
B. µ / Eds
C. µ x Eds
D. Eds / µ
Answer: B
Clarification: Velocity can be given as the product of electron or hole mobility(µ) and electric field(Eds). It gives the flow velocity which an electron attains due to electric field.

5. Eds is given by __________
A. Vds / L
B. L / Vds
C. Vds x L
D. Vdd / L
Answer: A
Clarification: Electric field(Eds) can be given as the ratio of Vds and L. Eds is the electric field created from drain to source due to volta Vds.

6. What is the mobility of proton or hole at room temperature?
A. 650 cm²/V sec
B. 260 cm²/V sec
C. 240 cm²/V sec
D. 500 cm²/V sec
Answer: C
Clarification: The value of mobility of proton or hole at room temperature is 240 cm²/V sec. This gives the measure of how fast an electron can move.

7. In resistive region __________
A. Vds greater than (Vgs – Vt)
B. Vds lesser than (Vgs – Vt)
C. Vgs greater than (Vds – Vt)
D. Vgs lesser than (Vds – Vt)
Answer: B
Clarification: In non saturated or resistive region, Vds lesser than Vgs – Vt where Vds is the voltage between drain and source, Vgs is the gate-source voltage and Vt is the threshold voltage.

8. What is the condition for saturation?
A. Vgs = Vds
B. Vds = Vgs – Vt
C. Vgs = Vds – Vt
D. Vds > Vgs – Vt
Answer: B
Clarification: The condition for saturation is Vds = Vgs – Vt since at this point IR drop in the channel equals the effective gate to channel voltage at the drain.

9. Threshold voltage is negative for __________
A. nMOS depletion
B. nMOS enhancement
C. pMOS depletion
D. pMOS enhancement
Answer: A
Clarification: The threshold voltage for nMOS depletion denoted as Vtd is negative.

10. The current Ids _______ as Vds increases.
A. increases
B. decreases
C. remains fairly constant
D. exponentially increases
Answer: C
Clarification: The current Ids remains fairly constant as Vds increases in the saturation region.

11. In linear region ______ channel exists.
A. uniform
B. non-uniform
C. wide
D. uniform and wide
Answer: A
Clarification: In linear region of MOSFET, the channel is uniform and narrow. This is the concentration distribution.

12. When the channel pinches off?
A. Vgs > Vds
B. Vds > Vgs
C. Vds > (Vgs-Vth)
D. Vgs > (Vds-Vth)
Answer: C
Clarification: In MOSFET, in saturation region, when Vds > (Vgs – Vth), the channel pinches off that is the channel current at the drain spreads out.

13. When the threshold voltage is more, leakage current will be?
A. more
B. less
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: Increasing the threshold voltage, leads to small leakage current when turned off and reduces current flow when turned on.

14. MOSFET is used as ___________
A. current source
B. voltage source
C. buffer
D. divider
Answer: A
Clarification: MOSFET is used as current source. Bipolar junction transistor also acts as good current source.

VLSI Multiple Choice Questions on “Wiring Capacitances”.

1. Which contributes to the wiring capacitance?
A. fringing fields
B. interlayer capacitance
C. peripheral capacitance
D. all of the mentioned
Answer: D
Clarification: The sources of capacitances that contribute to the total wiring capacitance are fringing field capacitance, interlayer capacitance and peripheral capacitance.

2. What does the value d in fringing field capacitance measures?
A. thickness of wire
B. length of the wire
C. wire to substrate separation
D. wire to wire separation
Answer: C
Clarification: The quantity d in fringing field capacitance measures the wire to substrate separation. It is the distance between the wire and the substrate used in the device.

3. Total wire capacitance is equal to ___________
A. area capacitance
B. fringing field capacitance
C. area capacitance + fringing field capacitance
D. peripheral capacitance
Answer: C
Clarification: Total wire capacitance can be given as the sum of area capacitance and fringing field capacitance.

4. Interlayer capacitance occurs due to ___________
A. separation between plates
B. electric field between plates
C. charges between plates
D. parallel plate effect
Answer: D
Clarification: Interlayer capacitance occurs due to a parallel plate effect between one layer and another. When one capacitance value comes closer to another they create some combined effects.

5. Which capacitance must be higher?
A. metal to polysilicon capacitance
B. metal to substrate capacitance
C. metal to metal capacitance
D. diffusion capacitance
Answer: A
Clarification: Metal to polysilicon capacitance should be higher than metal to substrate capacitance. This is due to that when one layer underlies the other and in consequence interlayer capacitance is highly dependent on layout.

6. Peripheral capacitance is given in _________ eper unit length.
A. nano farad
B. pico farad
C. micro farad
D. farad
Answer: B
Clarification: Peripheral capacitance is given in picofarads per unit length. This is the sidewall capacitance. Each diode has this side wall capacitance.

7. For greater relative value of peripheral capacitance ___________ should be small.
A. source area
B. drain area
C. source & drain area
D. none of the mentioned
Answer: C
Clarification: The smaller the source or drain area, the greater the relative value of peripheral capacitance as they are both inversely related.

8. Diffusion capacitance is equal to ___________
A. area capacitance
B. peripheral capacitance
C. fringing field capacitance
D. area capacitance + peripheral capacitance
Answer: D
Clarification: Diffusion capacitance is given by the sum of area capacitance and peripheral capacitance.

9. Polysilicon is suitable for ___________
A. small distance
B. large distance
C. all of the mentioned’
D. none of the mentioned
Answer: A
Clarification: Polysilicon is unsuitable for routing Vdd or Vss other than for very small distance because of the relatively high Rs value of the polysilicon layer.

10. Which has a high voltage drop?
A. metal layer
B. polysilicon layer
C. diffusion layer
D. silicide layer
Answer: B
Clarification: Polysilicon layer has high voltage drop. It has a moderate RC product.

11. Which layer has high capacitance value?
A. metal
B. diffusion
C. silicide
D. polysilicon
Answer: B
Clarification: Diffusion or active layer has high capacitance value due to which it has low or moderate IR drop.

12. Which layer has high resistance value?
A. polysilicon
B. silicide
C. diffusion
D. metal
Answer: A
Clarification: Polysilicon layer has high resistance value and due to this it has high IR drop.

13. While measuring the output load capacitance Cgs, n and Cgs, p is not considered. Why?
A. Because Cgs, n and Cgs, p are the capacitances at the input nodes
B. Because Cgs, n and Cgs, p does not exist during the operation of CMOS inverter
C. Because Cgs, n and Cgs, p are storing opposite charges and cancel out each other during the calculation of load capacitance
D. None of the mentioned
Answer: A
Clarification: Cgs, n and Cgs, p are gate to source capacitances of nMOS and pMOS transistors in CMOS inverter. They are measured at input node. Therefore they are not considered for calculation of load capacitance.

14. During the calculation of load capacitance of a 1st stage CMOS inverter, the input node capacitances, Cgs, n and Cgs, p of the 2nd stage CMOS inverter is also considered.
A. True
B. False
Answer: B
Clarification: Instead thin oxide capacitance over the gate area is used for calculation.

VLSI Multiple Choice Questions on “Clocked Sequential Circuits”.

1. Clocked sequential circuits are
A. two phase overlapping clock
B. two phase non overlapping clock
C. four phase overlapping clock
D. four phase non overlapping clock
Answer: B
Clarification: Clocked sequential circuits are two phase non overlapping clock signals. Clock signals are distributed in two wires and it is non overlapping.

2. Which are easier to design?
A. clocked circuits
B. asynchronous sequential circuits
C. clocked circuits with buffer
D. asynchronous sequential circuits with buffers
Answer: A
Clarification: Clocked circuitry are easier to design than the asynchronous sequential circuits. But it is slower than the asynchronous sequential circuit.

3. ___________ is used to drive high capacitance load.
A. single polar capability
B. bipolar capability
C. tripolar capability
D. bi and tri polar capability
Answer: B
Clarification: Bipolar capability is used to drive high capacitance load. It can handle high loads as it is done by BiCMOS NAND gate logic.

4. As the temperature is increased, storage time ____________
A. halved
B. doubled
C. does not change
D. tripled
Answer: A
Clarification: As the temperature is increased, storage time is halved. It is inversely proportional to the storage time.

5. Inverting dynamic register element consists of __________ transistors for nMOS and _________ for CMOS.
A. two, three
B. three, two
C. three, four
D. four, three
Answer: C
Clarification: Dynamic register element consists of three transistors for nMOS and four for CMOS.

6. Non inverting dynamic register storage cell consists of _________ transistors for nMOS and _________ for CMOS.
A. six, eight
B. eight, six
C. five, six
D. six, five
Answer: A
Clarification: Non inverting dynamic register storage cell consists of six transistors for nMOS and eight for CMOS.

7. Register cell consists of
A. inverter
B. pass transistor
C. inverter & pass transistor
D. none of the mentioned
Answer: C
Clarification: Register cell consists of an inverter and a pass transistor or a transmission gate. Dynamic register cell consists of stick/circuit notation.

8. In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
A. series
B. cascade
C. parallel
D. series and parallel
Answer: B
Clarification: The basic inverters or nMOS transistors are connected in cascade to obtain four bit dynamic shift register.

9. In four bit dynamic shift register output is obtained
A. parallel output at inverters 1, 3, 5, 7
B. parallel output at inverters 1, 5, 8
C. parallel output at all inverters
D. parallel output at inverter 2, 4, 6, 8
Answer: D
Clarification: In four bit dynamic shift register, output is obtained parallelly at inverters 2, 4, 6, 8.

10. For signals which are updated frequently _____ is used.
A. static storage
B. dynamic storage
C. static and dynamic storage
D. buffer
Answer: B
Clarification: For signals which are updated frequently dynamic storage elements are used. It can be done at < 0.25 msec interval.

VLSI Multiple Choice Questions on “Design Using CIF Code”.

1. Caltech intermediate form code is a
A. low-level graphic language
B. low-level textual language
C. high-level graphic language
D. high-level textual language
Answer: A
Clarification: Caltech intermediate form code is a low-level graphic language used to specify geometry of integrated circuits.

2. CIF generates code which are
A. high-level language
B. assembly level language
C. machine readable language
D. very high-level language
Answer: C
Clarification: CIF code is to communicate chip geometry in a standard machine readable form for mask-making.

3. CIF code is compatible with
A. low system geometry
B. large system geometry
C. both low and large system geometry
D. medium system geometry
Answer: C
Clarification: CIF code is reasonable compact and can cope with both low and large system geometry. It is easily readable.

4. Design through CIF is done using
A. color codes
B. geometric shapes
C. different layer thickness
D. transistors
Answer: B
Clarification: In Caltech intermediate form code, the design is given using geometric shapes. Boxes, polygons and wires are readily defined.

5. The CIF dimensions are given in the form of
A. X,Y coordinates
B. lambda form
C. millimeter form
D. alpha form
Answer: A
Clarification: The CIF dimensions and positions are given in X, Y coordinate form but are in absolute dimension units and not in lambda form.

6. Polygons in CIF are specified in terms of
A. length
B. width
C. vertices
D. angles
Answer: C
Clarification: In CIF, polygons(P) are specified in terms of vertices in order. An n-sided polygon needs n vertices and a connection between first and last.

7. Wires are specified in terms of
A. vertices
B. width
C. angles
D. lengths
Answer: B
Clarification: Wires(W) are specified in terms of their width followed by the center line’s coordinates of the wire’s path.

8. CIF can also accommodate rotations and translations.
A. true
B. false
Answer: A
Clarification: CIF also accommodates cells and rotations and translations etc along with geometrical shaped designs.

9. If vector coordinate is (1,0) it indicates that
A. length is parallel to y-axis
B. length is parallel to x-axis
C. width is parallel to y-axis
D. width is parallel to x-axis
Answer: B
Clarification: If the vector coordinate is (1,0), it denotes that the length will be parallel to the x-axis. The direction is always assumed parallel to the length.

10. In which layer the geometrical structures exist?
A. metal
B. silicon
C. silicide
D. diffusion
Answer: B
Clarification: In CIF design is done using geometrical structures like boxes, polygons, etc and these boxes exist in the silicon layer.

VLSI Multiple Choice Questions on “Counters and Finite State Machines”.

1. Counters detect only bridging faults.
A. true
B. false
Answer: B
Clarification: Counters detect gate level struck-at faults and bridging faults of the circuit under test.

2. How many test patterns are required to test the circuit using counters?
A. 2ⁿ
B. 2^(n-1)
C. 2ⁿ – 1
D. 2ⁿ + 1
Answer: A
Clarification: A n-bit counter, generates 2 ⁿ possible test patterns which is sufficient to completely test n-bit combinational logic circuit with no feedback.

3. The desired N value for counters is
A. less than 50
B. less than 10
C. less than 25
D. less than 70
Answer: C
Clarification: The testing using counter method is practical for lesser value of N such as within 22 to 25 since for higher values of N more number of clock cycles are necessary.

4. The least significant bit toggles for
A. every clock cycle
B. every alternate clock cycle
C. every two clock cycles
D. every four clock cycles
Answer: A
Clarification: The least significant bit toggles every clock cycle and the most significant bit toggles every half way through and at the end of the count sequence.

5. Finite state machines are used for
A. deterministic test patterns
B. algorithmic test patterns
C. random test patterns
D. pseudo random test patterns
Answer: B
Clarification: Finite state machines are used for algorithmic test pattern generation testing for the circuit under test.

6. Address ordering minimizes the logic of finite state machines.
A. true
B. false
Answer: A
Clarification: Address ordering either ascending or descending order in the first and last loop minimizes the logic of finite state machines.

7. In finite state machine the data in and data out are
A. in same ports
B. different ports
C. same register
D. different register
Answer: B
Clarification: In finite state machine, there are separate ports for DATA IN and DATA OUT and this is a typical RAM structure.

8. _______ is used to control the read and write operations.
A. active low synchronous reset
B. active high synchronous reset
C. active low synchronous preset
D. active high synchronous preset
Answer: B
Clarification: With the use of active high synchronous reset (clear) read and write operations in a finite state machine can be done.

9. Finite state machine will initially set to all zeroes.
A. true
B. false
Answer: A
Clarification: Finite state machine has initial state initialized with all 0’s whereas LFSR and CA has initial state with any state other than all 0’s.

10. Fault coverage is ______ in finite state machines.
A. less
B. more
C. equal
D. none of the mentioned
Answer: B
Clarification: The fault coverage and area overhead is better when the initial state is initialized to all 0’s in finite state machine.

VLSI Questions and Answers for Aptitude test focuses on “GaAs Fabrication -3”.

1. Which has a lightly doped channel?
A. E-MOSFET
B. D-MOSFET
C. E-JFET
D. CE-JFET
Answer: A
Clarification: The E-MOSFET structure is similar to that of D-MOSFET except for a shallower and more lightly doped channel.

2. To begin conduction, E-MOSFET requires
A. negative gate voltage
B. positive gate voltage
C. negative drain voltage
D. positive drain voltage
Answer: B
Clarification: In E-MOSFET channel is in pinch-off at zero gate voltage. A positive gate voltage is required for the channel to begin conduction.

3. Wafer preparation takes place in
A. first-level metal phase
B. second-level metal phase
C. encapsulation phase
D. ion implantation phase
Answer: C
Clarification: Encapsulation phase is the first phase and it includes wafer preparation. Encapsulation is a process of deposition of first-level insulator Si₃N₄.

4. Steps involved in ion implantation phase is
A. metallization
B. anneal
C. alignment mark mask
D. lift-off
Answer: B
Clarification: Anneal is a process involved in ion implantation phase along with other processes like si+ implant mask, channel implant, source drain mask, etc.

5. For the formation of E-MESFET _______ is used.
A. n- implantation
B. n+ implantation
C. p- implantation
D. p+ implantation
Answer: A
Clarification: A n- implantation is used for formation of E-MESFET and n+ implantation for the formation of D-MESFET.

6. To activate a dopant, _______ is necessary.
A. low temperature stable gate
B. low temperature stable drain
C. high temperature stable gate
D. high temperature stable drain
Answer: C
Clarification: The anneal cycle requires a stable temperature of 850 degree celcius to activate the dopants it is necessary to choose high temperature stable gate.

7. The voltage swing for schottky barrier gate should be
A. low
B. high
C. very high
D. very low
Answer: A
Clarification: Schottky barrier gates on GaAs cannot be forward biased above 0.7 to 0.8 volt, the permissible voltage swing should be relatively low.

8. The E-MESFET is defined by intersection of
A. red and yellow masks
B. green and red masks
C. brown and red masks
D. green and yellow masks
Answer: B
Clarification: E-MESFET is defined by intersection of green and red masks and D-MESFET is defined by intersection of green, red and yellow masks.

9. E-JFET technology has
A. low voltage swing
B. high current swing
C. high power requirements
D. high voltage swing
Answer: D
Clarification: E-JFET technology for ultra high speed VLSI has reduced power requirements with larger logic voltage swings.

10. In a CE-JFET, the ratio of electron mobility to hole mobility is equal to
A. 4
B. 10
C. 5
D. 20
Answer: B
Clarification: In a CE-JFET, the ratio of effective channel electron mobility of the n-channel device to hole mobility of the p-channel device is equal to 10.

11. Equal number of p and n devices in a device will consume
A. small area
B. large area
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: The circuits requiring equal numbers of p and n devices will consume large areas. Thus one must use other design methods such as precharge techniques.

12. In high electron mobility transistor, the electrons are
A. far apart
B. high mobility
C. near by and low mobility
D. far apart and high mobility
Answer: B
Clarification: The electrons in high electron mobility transistor are spacially separated from ionized donors and they exhibit high mobility.

f VLSI for Aptitude test,