Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “FET”.

1. Field effect transistor uses ________ to control the shape.
A. electric field
B. magnetic field
C. current distribution
D. voltage distribution
Answer: A
Clarification: Field effect transistor uses electric field to control the shape and hence the electrical conductivity of the channel.

2. Field effect transistors are known as
A. unipolar device
B. bipolar device
C. tripolar device
D. multipolar device
Answer: A
Clarification: Field effect transistors are unipolar transistors as they involve single-carrier-type operation.

3. The FET has __________ input impedance.
A. low
B. high
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: Field effect transistors have high input impedance. The conductivity of non-FET transistors are regulated by the input current thus it has low input impedance.

4. Field effect transistor’s conductivity is regulated by
A. input current
B. output current
C. terminal voltage
D. supply voltage
Answer: C
Clarification: Field effect transistor’s conductivity is regulated by the voltage applied to a terminal (the gate) which is insulated from the device.

5. In FET, the current enters the channel through
A. source
B. drain
C. gate
D. nodes
Answer: A
Clarification: In field effect transistor, the current enters the channel through source and the current leaves the junction through drain.

6. Which terminal bias the transistor to operation?
A. source
B. drain
C. gate
D. base
Answer: D
Clarification: Other than the three terminals, source drain and gate, there is a fourth terminal called as body or base. This is used to bias the transistor to operation.

7. In FET, the width is greater than the length of the gate.
A. true
B. false
Answer: A
Clarification: In FET, the width is greater than the length of the gate. Length gives the distance between source and drain. Width is the extension of the transistor, in the direction perpendicular to cross section.

8. Which terminal controls the electron flow passage?
A. source
B. drain
C. gate
D. base
Answer: C
Clarification: Gate permits the electron to flow through or block their passage by creating or eliminating the channel between source and drain.

9. The expansion of depletion region in n-channel device makes the channel
A. narrow
B. wide
C. does not affect the channel
D. cannot be determined
Answer: A
Clarification: In n-channel depletion mode device, as the depletion region width expands, it encroaches the channel from the sides and the channel becomes narrow.

10. Which voltage increases the channel size?
A. negative Vgs
B. positive Vgs
C. negative Vds
D. positive Vds
Answer: B
Clarification: A positive gate to source voltage increases the channel size and allows the electrons to flow easily.

11. Which relation is correct?
A. Vgs greater than Vds
B. Vds greater than Vgs
C. Vds equal to Vgs
D. Vgs lesser than Vds
Answer: A
Clarification: In FET, for either depletion or enhancement mode device the drain to source voltage is much less than the gate to source voltage.

12. Which mode of operation of FET is used, when amplification is needed?
A. active
B. saturation
C. non saturation
D. linear
Answer: B
Clarification: Saturation mode, which is in between the ohmic and saturation region is used when amplification is needed.

VLSI Multiple Choice Questions on “Basic MOS Transistors-1”.

1. Electronics are characterized by ____________
A. low cost
B. low weight and volume
C. reliability
D. all of the mentioned
Answer: D
Clarification: Electronics are characterized by reliability, low power dissipation, extremely low weight and volume, low cost, can cope up with high degree of sophistication and complexity.

2. Speed power product is measured as the product of ____________
A. gate switching delay and gate power dissipation
B. gate switching delay and gate power absorption
C. gate switching delay and net gate power
D. gate power dissipation and absorption
Answer: A
Clarification: Speed power product is measure in picojoules and it is the product of gate switching delay and gate power dissipation.

3. nMOS devices are formed in ____________
A. p-type substrate of high doping level
B. n-type substrate of low doping level
C. p-type substrate of moderate doping level
D. n-type substrate of high doping level
Answer: C
Clarification: nMOS devices are formed in a p-type substrate of moderate doping level. nMOS devices have higher mobility and is cheaper.

4. Source and drain in nMOS device are isolated by ____________
A. a single diode
B. two diodes
C. three diodes
D. four diodes
Answer: B
Clarification: The source and drain regions are formed by diffusing n-type impurity, it gives rise to depletion region which extend in more lightly doped p-region. Thus Source and drain in an nMOS device are isolated by two diodes.

5. In depletion mode, source and drain are connected by ____________
A. insulating channel
B. conducting channel
C. Vdd
D. Vss
Answer: B
Clarification: In depletion mode, source and drain are connected by conducting channel but the channel can be closed by applying suitable negative voltage to the gate.

6. What is the condition for non saturated region?
A. Vds = Vgs – Vt
B. Vgs lesser than Vt
C. Vds lesser than Vgs – Vt
D. Vds greater than Vgs – Vt
Answer: C
Clarification: The condition for non saturated region is Vds lesser Vgs – Vt. In non saturation region, MOSFET acts as voltage source. Varying Vds will provide a significant change in drain current.

7. In enhancement mode, device is in _________ condition.
A. conducting
B. non conducting
C. partially conducting
D. insulating
Answer: B
Clarification: In enhancement mode, the device is in non conducting condition. For n-type FET, the threshold voltage is positive and p-type threshold voltage is negative.

8. What is the condition for non conducting mode?
A. Vds lesser than Vgs
B. Vgs lesser than Vds
C. Vgs = Vds = 0
D. Vgs = Vds = Vs = 0
Answer: D
Clarification: In enhancement mode the device is in non conducting mode, and its condition is Vds = Vgs = Vs = 0.

9. nMOS is ____________
A. donor doped
B. acceptor doped
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: nMOS transistors are acceptor doped. Acceptor is a dopant which when added forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.

10. MOS transistor structure is ____________
A. symmetrical
B. non symmetrical
C. semi symmetrical
D. pseudo symmetrical
Answer: A
Clarification: MOS transistor structure is completely symmetrical with respect to source and drain.

11. pMOS is ____________
A. donor doped
B. acceptor doped
C. all of the mentioned
D. none of the mentioned
Answer: A
Clarification: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms p-type region and donor doped forms n-type region.

12. Inversion layer in enhancement mode consists of excess of ____________
A. positive carriers
B. negative carriers
C. both in equal quantity
D. neutral carriers
Answer: B
Clarification: Inversion layer in enhancement mode consists of excess of negative carriers that is electron.

13. What is the condition for linear region?
A. Vgs lesser than Vt
B. Vgs greater than Vt
C. Vds lesser than Vgs
D. Vds greater than Vgs
Answer: B
Clarification: The condition for linear region is Vgs > Vt. The power of MOS in the linear region is less. It is a power dissipating region.

14. As source drain voltage increases, channel depth ____________
A. increases
B. decreases
C. logarithmically increases
D. exponentially increases
Answer: B
Clarification: As source drain voltage Vds increases, the channel depth at the drain end decreases.

VLSI Multiple Choice Questions on “Design Rules and Layout-1”.

1. Circuit design concepts can also be represented using a symbolic diagram.
A. true
B. false
Answer: A
Clarification: Circuit design concepts can be represented using stick diagrams and symbolic diagrams. Stick diagrams represents different layers with color codes. Symbolic diagram represents the structure with symbols with color codes.

2. Circuit designers need _______ circuits.
A. tighter
B. smaller layout
C. decreased silicon area
D. all of the mentioned
Answer: D
Clarification: Circuit designers in general prefer tighter, smaller layouts for improved performance and decreased silicon area.

3. Process engineers want ______ process.
A. smaller
B. tighter
C. reproducible
D. non reproducible
Answer: C
Clarification: Process engineers want design rules which are controllable and reproducible process.

4. Maturity level of the process line affects design rules.
A. true
B. false
Answer: A
Clarification: Yes, the maturity level of the process line affects design rules.

5. Design rules does not specify __________
A. linewidths
B. separations
C. extensions
D. colours
Answer: D
Clarification: Design rules specify line widths, separations and extensions in terms of lambda.

6. The width of n-diffusion and p-diffusion layer should be?
A. 3λ
B. 2λ
C. λ
D. 4λ
Answer: B
Clarification: The width of n-diffusion and p-diffusion should be 2λ according to design rules.

7. What should be the spacing between two diffusion layers?
A. 4λ
B. λ
C. 3λ
D. 2λ
Answer: C
Clarification: The spacing between two diffusion layers should be 3λ according to design rules and standards.

8. What should be the width of metal 1 and metal 2 layers?
A. 3λ, 3λ
B. 2λ, 3λ
C. 3λ, 4λ
D. 4λ, 3λ
Answer: C
Clarification: The width of the metal 1 layer should be 3λ and metal 2 should be 4λ.

9. Implant should extend _______ from all the channels.
A. 2λ
B. 3λ
C. 4λ
D. λ
Answer: A
Clarification: Implant for a n-mos depletion mode transistor should extend minimum of 2λ from the channel in all the directions.

10. Which type of contact cuts are better?
A. buried contacts
B. butted contacts
C. butted & buried contacts
D. none of the mentioned
Answer: A
Clarification: Buried contacts are much better than butted contacts. In butted contacts the two layers are joined together or binded together using adhesive type of material where as in buried contact one layer is interconcted or fitted into another.

11. Which design method occupies or uses lesser area?
A. lambda rules
B. micron rules
C. layer rule
D. source rule
Answer: B
Clarification: Micron rules occupies or consumes lesser area. 50% of the area usage can be reduced by using micron rules over lambda rules.

12. Which gives scalable design rules?
A. lambda rules
B. micron rules
C. layer rules
D. thickness rules
Answer: A
Clarification: Lambda rules gives scalable design rules and micron rules gives absolute dimensions.

13. Devices designed with lambda design rules are prone to shorts and opens.
A. true
B. false
Answers: b
Clarification: Lambda design rules prevent shorting, opens, contact from slipping out of the area to be contacted.

VLSI Multiple Choice Questions on “Flash memory “.

1. Flash memory is a non-volatile storage device in which data
A. can be erased physically
B. can be erased magnetically
C. can be erased electrically
D. cannot be erased
Answer: C
Clarification: Flash memory is an electronic, solid state, non-volatile memory storage device which can be electrically erased and reprogrammed.

2. NOR type flash allows ______ to be read or written independently.
A. one machine cycle
B. one machine word
C. one machine sentence
D. one bit
Answer: B
Clarification: NOR type flash allows a single machine word that is one byte to be written to an erased location or read independently.

3. NAND type flash memories are used in
A. Memory cards
B. USB
C. Solid state drivers
D. All of the mentioned
Answer: D
Clarification: NAND type flash memories operates primarily in memory cards, USB flash drives and solid state drivers.

4. Which is a comparatively slower device?
A. ROM
B. RAM
C. flash memory
D. SRAM
Answer: C
Clarification: Flash memory has fast read access time, but static RAM or ROM are comparatively faster than flash memory.

5. Floating gate transistor in flash memory has
A. two gates
B. one gate
C. two sources
D. two drains
Answer: A
Clarification: Floating gate transistor in flash memory has two gates. These two gates are – floating gate and control gate.

6. In NOR type flash memory, each cell has one end connected to
A. source
B. drain
C. gate
D. ground
Answer: D
Clarification: In NOR type flash memory, each cell has one end connected directly to ground and other end connected to the bit line.

7. In NOR type flash memory, data is erased
A. bitwise
B. bytewise
C. blockwise
D. sentence wise
Answer: C
Clarification: In NOR type flash memory the data can be erased only blockwise basis. all the cells in an erase segment must be erased together.

8. The transistors in NAND type flash are connected in
A. series
B. parallel
C. cascade
D. randomly
Answer: A
Clarification: The NAND type flash memory also uses floating gate transistors and it is connected to form NAND gate. The transistors are connected in series.

9. In NAND type flash, memory can be addressed bit-wise.
A. true
B. false
Answer: A
Clarification: In NAND type flash, memory can be addressed by word, page or even bit wise. In NOR type flash, memory can be addressed by page then a word.

10. The program erase cycle in flash memory is
A. finite
B. infinite
C. all of the mentioned
D. none of the mentioned
Answer: A
Clarification: One disadvantage of flash memory is that it has finite number of program-erase cycles. This limits the usage of flash memory.

11. NOR type flash needs error correcting code.
A. true
B. false
Answer: B
Clarification: NOR flash memory is a storage device. It has slow write speed compared to NAND type flash. Typical NOR type flash does not need error correcting codes.

12. Which allows random access to read?
A. NOR type flash
B. NAND type flash
C. all of the mentioned
D. none of the mentioned
Answer: A
Clarification: The interface provided for reading and writing is different. NOR type flash provides random access for reading whereas NAND type flash provides page access.

13. Which has high storage capacity?
A. NOR type flash
B. NAND type flash
C. all of the mentioned
D. none of the mentioned
Answer: B
Clarification: NAND type flash memory has different connections and interface when compared to NOR type flash. Storage capacity is more in NAND type flash than NOR type flash memory.

VLSI Mcqs focuses on “Guidelines for Testability -3”.

1. Counters are
A. sequential circuits
B. synchronous circuits
C. asynchronous circuits
D. buffer circuits
Answer: A
Clarification: Counters are sequential circuits and need a large number of input vectors to be fully tested.

2. Wrong readings are recorded due to reset input being
A. dependent of clock signal
B. independent of clock signal
C. dependent of gate signal
D. independent of gate signal
Answer: B
Clarification: Since reset input is independent of system clock signal, erroneous readings are being read by the tester.

3. To avoid self resetting, the tester can be over ridden by adding
A. an AND gate
B. an OR gate
C. an EX-OR gate
D. shift registers
Answer: B
Clarification: Self resetting can be avoided by adding an OR gate which over rides the tester.

4. Partitioning technique is not suitable for microprocessor like circuits.
A. true
B. false
Answer: B
Clarification: Partitioning technique is very widely used for microprocessor like circuits and using bus structures is related to partitioning technique.

5. The fast rise and fall times give cross-talk problems if
A. they are in close proximity
B. if they are far away
C. it always gives rise to croo-talk problems
D. does not allow croo-talk problems
Answer: A
Clarification: The fast rise and fall times of digital signals can give rise to croo-talk problems in analog signal lines if they are in close proximity.

6. To route digital signals near analog signals _______ must be done.
A. balancing
B. shielding digital signals
C. balancing and shielding
D. crossing
Answer: C
Clarification: To route digital signals near analog signals, balancing and shielding of digital signals must be done.

7. To access directly another system ______ is done.
A. skipping
B. alternating
C. by-passing
D. by-setting
Answer: C
Clarification: To directly access another sub-system to be tested from one subsystem, by-passing must be performed.

8. With partitioning, bypassing is performed using
A. buffers
B. multiplexers
C. multipliers
D. dividers
Answer: B
Clarification: With partitioning, to directly access a sub-system for testing, bypassing must be done and this is achieved using multiplexers.

9. Bypassing technique works well with
A. dividers
B. counters
C. RAM
D. all of the mentioned
Answer: D
Clarification: Bypassing technique works well with counters, dividers, RAM, ROM, PLAs, sequential blocks, analog circuits and internal clocks.

10. In the bypassing approach, subsystem can be tested
A. exhaustively
B. pseudo-exhaustively
C. repeatedly
D. selectively
Answer: A
Clarification: In the bypassing approach, subsystem can be tested exhaustively by controlling the multiplexers based interconnections in the system.

MCQs on all areas of VLSI,