Category: VLSI Objective Questions

VLSI Multiple Choice Questions on “Latch-up in CMOS”.

1. In latch-up condition, parasitic component gives rise to __________ conducting path.
A. low resistance
B. high resistance
C. low capacitance
D. high capacitance
Answer: A
Clarification: In latch-up condition, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.

2. Latch-up can be induced by __________
A. incident radiation
B. reflected radiation
C. etching
D. diffracted radiation
Answer: A
Clarification: Latch-up can be induced by glitches on the supply rail or by incident radiation.

3. How many transistors might bring up latch up effect in p-well structure?
A. two
B. three
C. one
D. four
Answer: A
Clarification: Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.

4. Substrate doping level should be decreased to avoid the latch-up effect.
A. true
B. false
Answer: B
Clarification: An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for latch-up problem.

5. What can be introduced to reduce the latch-up effect?
A. latch-up rings
B. guard rings
C. latch guard rings
D. substrate rings
Answer: B
Clarification: The introduction of guard rings can reduce the effect of latch-up problem. Guard rings are diffusions which decouple the parasitic bipolar transistors.

6. Which process produces a circuit which is less prone to latch-up effect?
A. CMOS
B. nMOS
C. pMOS
D. BiCMOS
Answer: D
Clarification: BiCMOS process produces circuits that are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.

7. Which one of the following is the main factor for reducing the latch-up effect?
A. reduced p-well resistance
B. reduced n-well resistance
C. increased n-well resistance
D. increased p-well resistance
Answer: B
Clarification: One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher value of holding current is also required.

8. The parasitic PNP transistor has the effect of _______ carrier lifetime.
A. increasing
B. decreasing
C. exponentially decreasing
D. exponentially increasing
Answer: B
Clarification: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.

9. The reduction in carrier lifetime brings about __________
A. reduction in alpha
B. reduction in beta
C. reduction in current
D. reduction in voltage
Answer: B
Clarification: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.

10. To reduce latch-up effect substrate resistance should be high.
A. true
B. false
Answer: B
Clarification: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of Rs and Rw means that larger lateral current is necessary to invite latch-up.

11. Latch-up is the generation of __________
A. low impedance path
B. high impedance path
C. low resistance path
D. high resistance path
Answer: A
Clarification: Latch-up is the generation of low-impedance path in CMOS chips between the power supply and ground rails.

12. Latch-up is brought about by BJTs __________
A. with positive feedback
B. with negative feedback
C. with no feedback
D. without BJT
Answer: A
Clarification: Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short circuit the power and ground rail.

13. Sudden transient in power can cause latch-up.
A. true
B. false
Answer: A
Clarification: Sudden transient in power and ground buses are also among the reason which causes latch-up effect.

14. BJT gain should be ______ to avoid latch-up effect.
A. increased
B. decreased
C. should be maintained constant
D. changed randomly
Answer: B
Clarification: BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.

VLSI Multiple Choice Questions on “Scaling Factors -1”.

1. Microelectronic technology cannot be characterized by
A. minimum feature size
B. power dissipation
C. production cost
D. designing cost
Answer: D
Clarification: Microelectronic technology can be characterized by minimum feature size, number of gates on one chip, power dissipation, die size, production cost, etc and not by designing cost.

2. Which model is used for scaling?
A. constant electric scaling
B. constant voltage scaling
C. costant electric and voltage scaling
D. costant current model
Answer: C
Clarification: Constant electric scaling model and constant voltage scaling model is used for scaling.

3. α is used for scaling
A. linear dimensions
B. vdd
C. oxide thickness
D. non linear
Answer: A
Clarification: α is used as the scaling factor for linear dimensions where as β is used for supply voltage Vdd, gate oxide thickness etc.

4. For constant voltage model,
A. α = β
B. α = 1
C. α = 1/β
D. β = 1
Answer: D
Clarification: For constant voltage model, β = 1 and 1/β is chosen for the scaling for all voltages.

5. For constant electric field model,
A. β = α
B. α = 1
C. α = 1/β
D. β = 1
Answer: A
Clarification: For constant voltage model, β = α.

6. Gate area can be given as
A. L/W
B. L * W
C. 2L/W
D. L/2W
Answer: B
Clarification: Gate area Ag can be given as the product of length and the width of the channel.

7. Gate area is scaled by
A. α
B. 1/α
C. 1/α²
D. α²
Answer: C
Clarification: Gate area is given as the product of length and width of the channel and it can be scaled by 1/α².

8. Gate capacitance per unit area is scaled by
A. α
B. 1
C. 1/β
D. β
Answer: D
Clarification: Gate capacitance per unit area is scaled by β and this is given by €ox/D.

9. Parasitic capacitance is given by
A. Ax/d
B. Ax * d
C. d/Ax
D. Ax
Answer: A
Clarification: Parasitic capacitance is given by Ax/d where Ax is the area of the depletion region and d is the depletion width.

10. Parasitic capacitance is scaled by
A. β
B. 1/β
C. α
D. 1/α
Answer: D
Clarification: Parasitic capacitance is scaled by 1/α because area is scaled by 1/α² and d by 1/α. Thus (1/α²)/(1/α) we will get 1/α.

VLSI Multiple Choice Questions on “Multiplier Systems”.

1. Multipliers are built using
A. binary adders
B. binary subtractors
C. dividers
D. multiplexers
Answer: A
Clarification: A multiplier is an electronic circuit used to multiply two bianry numbers. It is built using binary adders that are full adders.

2. Which method uses reduced number of partial products?
A. Baugh-wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding
Answer: D
Clarification: Multiplication in multipliers is done by obtaining partial products and then summing it up. Modified booth encoding reduces the number of partial products that must be summed.

3. Which method is easier to manipulate accumulator content?
A. left shifting
B. right shifting
C. serial shifting
D. parallel shifting
Answer: B
Clarification: It is easier to right shift the contents of the accumulator than to left shift. This can be used to eliminate the least significant bits of the product.

4. Which multiplier is very well suited for twos-complement numbers?
A. Baugh-wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding
Answer: A
Clarification: Baugh-wooley method is used to design multipliers that are regular in structure and is very well suited for twos complement numbers.

5. What is the delay required to perform a single operation in a pipelined structure?
A. 2n
B. 3n
C. 4n
D. n
Answer: B
Clarification: The delay of one operation through the pipeline is 3n that is it takes 3n clock cycles to obtain a product after X and Y are input.

6. Latches choosen are
A. static shift registers
B. any flipflop
C. dynamic shift register
D. multiplexers
Answer: C
Clarification: The latches choosen are dynamic shift register as the structure will be continuously clocked.

7. Which method reduces number of cycles of operation?
A. Baugh-wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding
Answer: D
Clarification: Modified booth encoding algorithm avoids many idle cells in a cellular multiplier as well as reduces the number of cycles compared with the serial-parallel multiplier.

8. The completion time for multiplication time in baugh-wooley method is
A. n
B. 2n
C. 3n
D. 4n
Answer: B
Clarification: The completion time for multiplication in Braun or Baugh-wooley is proportional to 2n where as completion time in Wallace tree method is proportional to log(base 2)(n).

9. In which method minimum number of adder cells are used?
A. Baugh-wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding
Answer: C
Clarification: Dadda multipliers are similar to Wallace trees but it has a reduced number of adder cells. This is a technique developed from Wallace tree but with an improvement.

10. Which method is suitable for larger operands?
A. Baugh-wooley algorithm
B. Wallace trees
C. Dadda multipliers
D. Modified booth encoding
Answer: B
Clarification: Wallace tree multipliers should be used for larger operands and where the performance is critical.

VLSI Multiple Choice Questions on “Guidelines for Testability -1”.

1. Practical guidelines for testability aims at
A. facilitating test generation
B. facilitating test application
C. avoiding timing problems
D. all of the mentioned
Answer: D
Clarification: Practical guidelines for testability should aim to facilitate test process in three main ways – facilitate test generation, facilitate test application and avoid timing problems.

2. When a node is difficult to access
A. sub nodes are formed
B. internal pads are added
C. external pads are added
D. circuit is sub divided
Answer: B
Clarification: When a node is difficult to access from primary input or output pads, then a very effective method is to add additional internal pads to access the desired point.

3. The additional pads are accessed using
A. probers
B. selectors
C. multiplexers
D. buffers
Answer: A
Clarification: The additional pads which are added for the access of nodes, can be accessed using probers.

4. Which provides links between blocks of a circuit?
A. combiners
B. wires
C. pads
D. nodes
Answer: D
Clarification: A node provides the link between blocks of a circuit and the attributes provide the control of the blocks.

5. To improve controllability and observability ______ is used.
A. three pads
B. eight transistors
C. three pads and eight transistors
D. four pads and eight transistors
Answer: C
Clarification: In CMOS environment, three pads and eight transistors are required to improve controllability and observability.

6. The addition of ______ improves the observability.
A. adders
B. multiplexers
C. multipliers
D. demultiplexers
Answer: D
Clarification: The addition of demultiplexers also improves observability. This arrangement allows bypassing of blocks.

7. How to reduce test time?
A. by reducing multiplexers
B. by reducing adders
C. by dividing circuit into subcircuits
D. by using the whole circuit as a single system
Answer: C
Clarification: Partitioning large circuits into smaller subcircuits is an effective way of reducing test generation complexity and test time.

8. Test generation effort for n gate circuit is proportional to
A. n
B. n²
C. n³
D. n² and n³
Answer: D
Clarification: Test generation effort for a n gate general purpose logic circuit is proportional to n² and n³.

9. Patitioning should be made on a
A. logical basis
B. functional basis
C. time basis
D. structural basis
Answer: A
Clarification: Partitioning should be made on logical basis into recognizable and sensible subfunctions and can be done physically by incorporating clock line isolation and power supply lines.

10. Isolation and control is achieved using
A. adders
B. buffers
C. multiplexers
D. multipliers
Answer: C
Clarification: Isolation and control are better and readily achieved through the use of multiplexers.

VLSI Multiple Choice Questions on “Design for Testability”.

1. Design for testability is considered in production for chips because:
A. Manufactured chips are faulty and are required to be tested
B. The design of chips are required to be tested
C. Many chips are required to be tested within short interval of time which yields timely delivery for the customers
D. All of the mentioned
Answer: C
Clarification: Design for testability is considered in production for chips because many chips are required to be tested within short interval of time which yields timely delivery for the customers.

2. The functions performed during chip testing are:
A. Detect faults in fabrication
B. Detect faults in design
C. Failures in functionality
D. All of the mentioned
Answer: D
Clarification: The functions performed during chip testing are detecting faults in fabrication and design failures in functionality.

3. ATPG stands for:
A. Attenuated Transverse wave Pattern Generation
B. Automatic Test Pattern Generator
C. Aligned Test Parity Generator
D. None of the mentioned
Answer: B
Clarification: ATPG is an Automatic Test Pattern Generator.

4. Delay fault is considered as:
A. Electrical fault
B. Logical fault
C. Physical defect
D. None of the Mentioned
Answer: B
Clarification: Delay fault is considered a logical fault.

5. A metallic blob present between drain and the ground of the n-MOSFET inverter acts as:
A. Physical defect
B. Logical fault as output is stuck on 0
C. Electrical fault as resistor short
D. All of the mentioned
Answer: D
Clarification: A metallic blob present between drain and the ground of the n-MOSFET inverter acts as Physical defect, Logical fault as output is stuck on 0, Electrical fault as resistor short.

6. High resistance short present between drain and ground of n-MOSFET inverter acts as:
A. Pull up delay error
B. Logical fault as output is stuck at 1
C. Electrical fault as transistor stuck on
D. All of the mentioned
Answer: A
Clarification: High resistance short present between drain and ground of n-MOSFET inverter acts as Pull up delay error.

7. The defect present in the following MOSFET is:
vlsi-questions-answers-design-testability-q7″>
A. Logical stuck at 1
B. Logical stuck at 0
C. Physical defect
D. Electrical Transistor stuck open
Answer: D
Clarification: The dimensions of the gate is less than the distance between source and drain.

8. The fault simulation detects faults by:
A. Test generation
B. Construction of fault Dictionaries
C. Design analysis under faults
D. All of the mentioned
Answer: D
Clarification: None.

9. The ease with which the controller establishes specific signal value at each node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: C
Clarification: Controllability is defined as the ease with which the controller establishes specific signal value at each node by setting input values.

10. The ease with which the controller determines signal value at any node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: B
Clarification: Observability is defined as the ease with which the controller determines signal value at any node by setting input values.

11. The poor controllability circuits are:
A. Decoders
B. Clock generators
C. Circuits with feedback
D. All of the mentioned
Answer: D
Clarification: None.

12. The circuits with poor observability are:
A. ROM
B. PLA
C. Sequential circuits with long feedback loops
D. All of the mentioned
Answer: C
Clarification: None.

13. Large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output makes the circuit low on:
A. Testability
B. Observability
C. Controllability
D. All of the mentioned
Answer: A
Clarification: The circuit is said to be low on Testability if large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output.

14. Divide and Conquer approach to large and complex circuits for testing is found in:
A. Partition and Mux Technique
B. Simplified automatic test pattern generation technique
C. Scan based technique
D. All of the mentioned
Answer: A
Clarification: Divide and Conquer approach to large and complex circuits for testing is found in the partition and Mux technique.

15. LSSD stands for:
A. Linear system synchronous detection
B. Level sensitive system detection
C. Level sensitive scan design
D. Level sensitive scan detection
Answer: C
Clarification: None.

VLSI Problems focuses on ” MESFET Design-2″.

1. In the ring diagram, green line is used to represent
A. E-MESFET
B. D-MESFET
C. Interconnection
D. Transistor
Answer: A
Clarification: In the ring diagram, green or dotted line represents E-MESFET while yellow or solid line represents D-MESFET.

2. E-type and D-type is joined together using
A. metal 1
B. metal 2
C. vias
D. interconnectors
Answer: A
Clarification: E-type and D-type features are joined together using blue color which represents metal 1 layer.

3. What is the intermediate stage in converting ring diagram to mask layout?
A. switch logic
B. transistor level diagram
C. symbolic diagram
D. stick diagram
Answer: C
Clarification: The ring diagrams can be turned into mask layout directly or through an intermediate symbolic representation stage.

4. In symbolic representation, rings are converted into
A. color codes
B. switches
C. sticks
D. circuit elements
Answer: D
Clarification: Symbolic representation is the intermediate stage when turning ring diagram to mask layout and here rings are represented as circuit elements.

5. For inverters color code used is
A. red followed by green paths
B. green followed by red paths
C. green followed by yellow paths
D. red followed by yellow paths
Answer: C
Clarification: The green followed by yellow paths are drawn for inverters and inverter based logic such as NOR gates.

6. In symbolic representation _________ is used to represent E-MESFET.
A. red transistor
B. green transistor
C. yellow transistor
D. blue transistor
Answer: B
Clarification: In symbolic representation, green transistor is used to represent E-MESFET and yellow transistor is used to represent D-MESFET.

7. Global control paths are run in
A. metal 2
B. metal 1
C. transistor
D. interconnects
Answer: A
Clarification: Long signal and global control paths are run in metal 2 parallel with the power rails.

8. _______ gives the instruction for the preparation of photomasks.
A. design layout
B. design rules
C. color codes
D. layout map
Answer: B
Clarification: Design rules are the prescription for the preparation of photomasks that are to be used in the fabrication of integrated circuits.

9. Design rule is not influenced by maturity of property line.
A. true
B. false
Answer: A
Clarification: Design rules can also be influenced by maturity of the process line. If the process is mature, then one can be assured of the process line capability allowing tighter design with fewer constraints.

10. The separation between implant is determined from
A. width of transistor
B. width of E-MESFET
C. width of D-MESFET
D. width of photoresist
Answer: D
Clarification: The separation between implant is determined from width of depletion region and width of photoresist.

11. MESFETs should be positioned
A. horizontally
B. vertically
C. diagonally
D. randomly
Answer: A
Clarification: All MESFETs should be positioned horizontally owing to its anisotropic nature of GaAs which influences the threshold voltage of the device.

12. Saturated resistor is a
A. FET with schottky gate
B. FET without schottky gate
C. MESFET with schottky gate
D. MESFET without schottky gate
Answer: D
Clarification: The saturated resistor is a MESFET with the schottky gate removed. The preferred direction for layout is vertical.

13. MIM capacitor uses
A. metal 1
B. metal 2
C. metal 1 and metal 2
D. schottky gate
Answer: C
Clarification: The metal-insulator-metal (MIM) capacitor structure is simple using metal 1 and metal 2 as the plates of a parallel plate capacitor.

14. The mask is derived from the structural operation of masks.
A. true
B. false
Answer: B
Clarification: The mask is derived from the logical operation of the active layer masks. Some processes require isolation between devices to reduce their interaction.

f VLSI Problems,