VLSI Multiple Choice Questions on “Design for Testability”.
1. Design for testability is considered in production for chips because:
A. Manufactured chips are faulty and are required to be tested
B. The design of chips are required to be tested
C. Many chips are required to be tested within short interval of time which yields timely delivery for the customers
D. All of the mentioned
Answer: C
Clarification: Design for testability is considered in production for chips because many chips are required to be tested within short interval of time which yields timely delivery for the customers.
2. The functions performed during chip testing are:
A. Detect faults in fabrication
B. Detect faults in design
C. Failures in functionality
D. All of the mentioned
Answer: D
Clarification: The functions performed during chip testing are detecting faults in fabrication and design failures in functionality.
3. ATPG stands for:
A. Attenuated Transverse wave Pattern Generation
B. Automatic Test Pattern Generator
C. Aligned Test Parity Generator
D. None of the mentioned
Answer: B
Clarification: ATPG is an Automatic Test Pattern Generator.
4. Delay fault is considered as:
A. Electrical fault
B. Logical fault
C. Physical defect
D. None of the Mentioned
Answer: B
Clarification: Delay fault is considered a logical fault.
5. A metallic blob present between drain and the ground of the n-MOSFET inverter acts as:
A. Physical defect
B. Logical fault as output is stuck on 0
C. Electrical fault as resistor short
D. All of the mentioned
Answer: D
Clarification: A metallic blob present between drain and the ground of the n-MOSFET inverter acts as Physical defect, Logical fault as output is stuck on 0, Electrical fault as resistor short.
6. High resistance short present between drain and ground of n-MOSFET inverter acts as:
A. Pull up delay error
B. Logical fault as output is stuck at 1
C. Electrical fault as transistor stuck on
D. All of the mentioned
Answer: A
Clarification: High resistance short present between drain and ground of n-MOSFET inverter acts as Pull up delay error.
7. The defect present in the following MOSFET is:
vlsi-questions-answers-design-testability-q7″>
A. Logical stuck at 1
B. Logical stuck at 0
C. Physical defect
D. Electrical Transistor stuck open
Answer: D
Clarification: The dimensions of the gate is less than the distance between source and drain.
8. The fault simulation detects faults by:
A. Test generation
B. Construction of fault Dictionaries
C. Design analysis under faults
D. All of the mentioned
Answer: D
Clarification: None.
9. The ease with which the controller establishes specific signal value at each node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: C
Clarification: Controllability is defined as the ease with which the controller establishes specific signal value at each node by setting input values.
10. The ease with which the controller determines signal value at any node by setting input values is known as:
A. Testability
B. Observability
C. Controllability
D. Manufacturability
Answer: B
Clarification: Observability is defined as the ease with which the controller determines signal value at any node by setting input values.
11. The poor controllability circuits are:
A. Decoders
B. Clock generators
C. Circuits with feedback
D. All of the mentioned
Answer: D
Clarification: None.
12. The circuits with poor observability are:
A. ROM
B. PLA
C. Sequential circuits with long feedback loops
D. All of the mentioned
Answer: C
Clarification: None.
13. Large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output makes the circuit low on:
A. Testability
B. Observability
C. Controllability
D. All of the mentioned
Answer: A
Clarification: The circuit is said to be low on Testability if large number of input vectors are used to set a particular node (1) or (0), to propagate an error at the node to output.
14. Divide and Conquer approach to large and complex circuits for testing is found in:
A. Partition and Mux Technique
B. Simplified automatic test pattern generation technique
C. Scan based technique
D. All of the mentioned
Answer: A
Clarification: Divide and Conquer approach to large and complex circuits for testing is found in the partition and Mux technique.
15. LSSD stands for:
A. Linear system synchronous detection
B. Level sensitive system detection
C. Level sensitive scan design
D. Level sensitive scan detection
Answer: C
Clarification: None.