VLSI Multiple Choice Questions on “Drivers”.
1. For shorter delays ______ resistance should be used.
A. smaller
B. larger
C. does not depend on resistance
D. very large
Answer: A
Clarification: For shorter delays low resistance should be used as delay is directly proportional or related to resistance.
2. To reduce resistance value of inverters, channels must be made __________
A. wider
B. narrower
C. lenghthier
D. shorter
Answer: A
Clarification: Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. imply low L:W ratios and thus consequently an inverter to meet this need occupies a larger area.
3. As width increases, capacitive load __________
A. increases
B. decreases
C. does not change
D. exponentially increases
Answer: A
Clarification: As width of the channel increases, capacitive load also increases and with this the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.
4. Delay per stage for logic 0 to 1 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: A
Clarification: Delay per stage for logic 0 to 1 transition can be given as fƮ. With large f, N decreases but delay per stage increases.
5. Delay per stage for logic 1 to 0 transition can be given as __________
A. fƮ
B. 2fƮ
C. 3fƮ
D. 4fƮ
Answer: D
Clarification: Delay per stage for logic 1 to 0 transition can be given as 4fƮ. Using the delay for transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.
6. What is the total delay of an nMOS pair?
A. fƮ
B. 2fƮ
C. 5fƮ
D. 4fƮ
Answer: C
Clarification: Total delay of an nMOS pair is equal to 5fƮ. This can be calculated by knowing delay per stage, that is for two different transitions from 0 to 1 and vice versa.
7. What is the total delay of a CMOS pair?
A. 5fƮ
B. 7fƮ
C. 8fƮ
D. 4fƮ
Answer: B
Clarification: Total delay of an CMOS pair is equal to 7fƮ. This can be calculated by knowing thee delay per stage of CMOS.
8. The number of stages N can be given as ___________
A. ln(y)*ln(f)
B. ln(y)/ln(f)
C. ln(f)/ln(y)
D. ln(f)/ln(2y)
Answer: B
Clarification: The number of stages N can be given as ln(y)/ln(f). By knowing whether the number of stages N is even or odd we can calculate the total delay for nMOS, CMOS etc.
9. When number of stages N is even, the total delay for nMOS can be?
A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer: B
Clarification: When number of stages N is even, the total delay for nMOS can be given as 2.5NfƮ. This is calculated by using the formula (N/2)*5fƮ.
10. When number of stages N is even, the total delay for CMOS can be?
A. 1.5NfƮ
B. 2.5NfƮ
C. 3.5NfƮ
D. 4.5NfƮ
Answer: C
Clarification: When the number of stages N is even, the total delay for CMOS can be given as 3.5NfƮ. This is calculated by using the formula (N/2)*7fƮ.
11. In BiCMOS drivers, the input voltage Vbe is _______ on base width.
A. directly proportional
B. inversely proportional
C. logarithmically proportional
D. exponentially proportional
Answer: C
Clarification: In BiCMOS driver, the input voltage Vbe is logarithmically proportional to the base width Wb and on electron mobility.
12. Which has a larger value?
A. Tin
B. TL
C. Rc
D. None of the mentioned
Answer: A
Clarification: In BiCMOS drivers, the initial time Tin necessary to charge base emitter junction is larger than the time TL requires to charge the output load capacitance.
13. In BiCMOS driver, a good bipolar transistor should have ___________
A. low Rc
B. high hfe
C. high gm
D. all of the mentioned
Answer: D
Clarification: In BiCMOS drivers, a good bipolar transistor should have low Rc, high hfe, high gm, etc.