Digital Electronic/Circuits online quiz on “Flip Flops”.
1. What is an ambiguous condition in a NAND based S’-R’ latch?
A. S’=0, R’=1
B. S’=1, R’=0
C. S’=1, R’=1
D. S’=0, R’=0
Answer: D
Clarification: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.
2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
A. No change
B. Set
C. Reset
D. Forbidden
Answer: A
Clarification: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It remains in its prior state. This state is used for the storage of data.
3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
A. A D latch at each of its input
B. An inverter at each of its input
C. It can never be converted
D. Both a D latch and an inverter at its input
Answer: D
Clarification: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an inverter at its input as it’s operations will be complementary.
4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
A. The inputs of NOR latch are 0 but 1 for NAND latch
B. The inputs of NOR latch are 1 but 0 for NAND latch
C. The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
D. The output of NOR latch is 1 but 0 for NAND latch
Answer: A
Clarification: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.
5. The characteristic equation of S-R latch is ____________
A. Q(n+1) = (S + Q(n))R’
B. Q(n+1) = SR + Q(n)R
C. Q(n+1) = S’R + Q(n)R
D. Q(n+1) = S’R + Q'(n)R
Answer: A
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.
6. The difference between a flip-flop & latch is ____________
A. Both are same
B. Flip-flop consist of an extra output
C. Latches has one input but flip-flop has two
D. Latch has two inputs but flip-flop has one
Answer: C
Clarification: Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is provided to the latch.
7. How many types of flip-flops are?
A. 2
B. 3
C. 4
D. 5
Answer: C
Clarification: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.
8. The S-R flip flop consist of ____________
A. 4 AND gates
B. Two additional AND gates
C. An additional clock input
D. 3 AND gates
Answer: B
Clarification: The S-R flip flop consists of two additional AND gates at the S and R inputs of S-R latch.
9. What is one disadvantage of an S-R flip-flop?
A. It has no Enable input
B. It has a RACE condition
C. It has no clock input
D. Invalid State
Answer: D
Clarification: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State.
10. One example of the use of an S-R flip-flop is as ____________
A. Racer
B. Stable oscillator
C. Binary storage register
D. Transition pulse generator
Answer: C
Clarification: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary storage element. It functions as memory storage during the No Change State.
11. When is a flip-flop said to be transparent?
A. When the Q output is opposite the input
B. When the Q output follows the input
C. When you can see through the IC packaging
D. When the Q output is complementary of the input
Answer: B
Clarification: Flip-flop have the property of responding immediately to the changes in its inputs. This property is called transparency.
12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
A. The clock pulse is LOW
B. The clock pulse is HIGH
C. The clock pulse transitions from LOW to HIGH
D. The clock pulse transitions from HIGH to LOW
Answer: C
Clarification: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.
13. What is the hold condition of a flip-flop?
A. Both S and R inputs activated
B. No active S or R input
C. Only S is active
D. Only R is active
Answer: B
Clarification: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No Change State or Memory Storage state if a flip-flop.
14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________
A. SET
B. RESET
C. Clear
D. Invalid
Answer: B
Clarification: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.
15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________
A. Edge-detection circuit
B. NOR latch
C. NAND latch
D. Pulse-steering circuit
Answer: A
Clarification: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the edge-detection circuit.