250+ TOP MCQs on Generate Statement and Answers

This set of VHDL Question Paper on “Generate Statement”.

1. Generate statement is a _______ statement.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process
Answer: a
Clarification: Generate statement is a concurrent statement that can be used in architecture directly. It is similar to loop statement in case of sequential statement. It give designer the ability to create replicated structures.

2. There are _______ types of GENERATE statement in VHDL.
a) 2
b) 3
c) 4
d) 5
Answer: a
Clarification: There are 2 types of GENERATE statement in VHDL. One is FOR generate and other is IF generate. They can be used to replicate a structure or logic and to enable/disable a block. FOR can be used for iterative elaboration of a logic and IF can be used for conditional elaboration of some block.

3. A generate statement is generally associated with ________ modeling.
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and data flow
Answer: c
Clarification: A generate statement is usually associated with component instantiation which is a part of structural modeling. For example, the FOR generate can be used to instantiate arrays of components and similarly IF can be used to instantiate the component conditionally.

4. What is the correct syntax for FOR generate statement?
a)

label : FOR parameter IN range GENERATE
      begin
      declarations;
      concurrent statement
      END GENERATE label;

b)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      concurrent statement
      END GENERATE label;

c)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END GENERATE label;

d)

label : FOR parameter IN range GENERATE
      declarations;
      begin
      sequential statement
      END label GENERATE;

View Answer

Answer: b
Clarification: For defining a generate statement the for loop is used in conjunction with GENERATE keyword. The local declarations can be made inside a generate block. Please note that generate is a concurrent statement which can contain concurrent statements only.

5. Using a label is compulsory with a GENERATE statement.
a) True
b) False
Answer: a
Clarification: Unlike other statements of VHDL, using a label is compulsory in a GENERATE statement. This label should be unique for each different GENERATE. Moreover, this label can be used to end the generate statement as well.

6. Which of the following is a correct statement for IF generate statement?
a)

     IF condition GENERATE
     begin
     declarations;
     concurrent_statements;
     END GENERATE label;

b)

     label : IF condition GENERATE
     declarations;
     begin
     sequential_statements;
     END GENERATE label;

c)

     IF condition GENERATE
     declarations;
     begin
     sequential_stataements;
     END GENERATE label;

d)

     label : IF condition GENERATE
     declarations;
     begin
     concurrent_statements;
     END GENERATE label;

View Answer

Answer: d
Clarification: A label is compulsory with IF generate statement as well. However, IF is a sequential statement, but when used with GENERATE it includes concurrent statements. The declarative part and the staements part is separated by the keyword BEGIN.

7. FOR generate creates ____________ objects.
a) Dissimilar
b) Unique
c) Different
d) Similar
Answer: d
Clarification: The generate statement will instance an array of objects which are all of homogeneous type or similar. This allows to generate multiple objects with a single statement.

8. What is realized in the code given below?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_logic IS
GENERIC n : INTEGER := 8;
PORT (sig1 : bit_vector(n-1 DOWNTO 0);
             Sig2 : bit_vector(n-1 DOWNTO 0));
END my_logic;
ARCHITECTURE test OF my_logic IS
COMPONENT or2
   PORT(a0, a1 : IN BIT;
                z         : OUT BIT);
END COMPONENT or
BEGIN
ORARRAY : FOR i IN (n-1) DOWNTO 0 GENERATE
                   or_gate : or2
PORT MAP ( a0 => sig1(i),
                       A1 => sig2(i),
                         z => y(i));
END GENERATE ORARRAY;
END test;

a) 7- Bit parallel adder ignoring the carry
b) 7- Bit parallel adder including the carry
c) 8- Bit parallel adder ignoring the carry
d) 8- bit parallel adder including the carry
Answer: c
Clarification: Since, a generic is used to specify the length of the arry which is assigned a value 8. The loop iterates from 7 downto 0 that means 8 times. So, an array of OR gates is instantiated by using this code including 8 OR gates. So, it is 8 bit parallel adder ignoring the carry.

9. Which of the following is legal?
a)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     concurrent_statement; 
      END GENERATE;

b)

     label : FOR n IN 7 DOWNTO 0 GENERATE
     declarations;     
      concurrent_statement; 
      END GENERATE;

c)

    label : FOR n IN 7 DOWNTO 0 GENERATE
     begin
     declarations; 
     concurrent_statement; 
      END GENERATE;

d)

    label : FOR n IN 7 DOWNTO 0 GENERATE
    begin 
    concurrent_statement; 
     END GENERATE label;

View Answer

Answer: a
Clarification: If the generate statement has no local declaration which means it has only statement part then there is no need to use the BEGIN keyword. Also, label is compulsory for a generate statement but it is not mandatory to use a label at the end of the generate statement.

10. Generate statements can’t be nested.
a) True
b) False
Answer: b
Clarification: It is possible to nest multiple generate statements means we can use one generate statement inside another generate statement. This can be useful to generate to dimensional or multi-dimensional arrays.

11. Which of the following is not possible to use inside the FOR generate statement?
a) IF
b) IN
c) EXIT
d) PORT MAP
Answer: c
Clarification: It is not possible to terminate the loop early in the case of generate statement. So, no such statement can be used inside the loop which can cause it to terminate early. Therefore, such statements like EXIT, BREAK etc. can’t be used.

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