Digital Electronics/Circuits Multiple Choice Questions on “Half Adder & Full Adder”.
1. In parts of the processor, adders are used to calculate ____________
A. Addresses
B. Table indices
C. Increment and decrement operators
D. All of the Mentioned
Answer: D
Clarification: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.
2. Total number of inputs in a half adder is __________
A. 2
B. 3
C. 4
D. 1
Answer: A
Clarification: Total number of inputs in a half adder is two. Since an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.
3. In which operation carry is obtained?
A. Subtraction
B. Addition
C. Multiplication
D. Both addition and subtraction
Answer: B
Clarification: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).
4. If A and B are the inputs of a half adder, the sum is given by __________
A. A AND B
B. A OR B
C. A XOR B
D. A EX-NOR B
Answer: C
Clarification: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.
5. If A and B are the inputs of a half adder, the carry is given by __________
A. A AND B
B. A OR B
C. A XOR B
D. A EX-NOR B
Answer: A
Clarification: If A and B are the inputs of a half adder, the carry is given by: A(AND.B, while the sum is given by A XOR B.
6. Half-adders have a major limitation in that they cannot __________
A. Accept a carry bit from a present stage
B. Accept a carry bit from a next stage
C. Accept a carry bit from a previous stage
D. Accept a carry bit from the following stages
Answer: C
Clarification: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.
7. The difference between half adder and full adder is __________
A. Half adder has two inputs while full adder has four inputs
B. Half adder has one output while full adder has two outputs
C. Half adder has two inputs while full adder has three inputs
D. All of the Mentioned
Answer: C
Clarification: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.
8. If A, B and C are the inputs of a full adder then the sum is given by __________
A. A AND B AND C
B. A OR B AND C
C. A XOR B XOR C
D. A OR B OR C
Answer: C
Clarification: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.
9. If A, B and C are the inputs of a full adder then the carry is given by __________
A. A AND B OR (A OR B. AND C
B. A OR B OR (A AND B. C
C. (A AND B. OR (A AND B.C
D. A XOR B XOR (A XOR B. AND C
Answer: A
Clarification: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B. AND C, which is equivalent to (A AND B. OR (B AND C. OR (C AND A..
10. How many AND, OR and EXOR gates are required for the configuration of full adder?
A. 1, 2, 2
B. 2, 1, 2
C. 3, 1, 2
D. 4, 0, 1
Answer: B
Clarification: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.