250+ TOP MCQs on Implementing Combinational Circuits with VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Implementing Combinational Circuits with VHDL – 1”.

1. Which of the following is a not a characteristics of combinational circuits?
a) The output of combinational circuit depends on present input
b) There is no use of clock signal in combinational circuits
c) The output of combinational circuit depends on previous output
d) There is no storage element in combinational circuit
Answer: c
Clarification: A combinational circuit is the one which has no storage of previous output. The next state or output of the combinational circuit depends only on its present input and hence no clock signal is required.

2. Sequential code can’t be used to design combinational circuit.
a) True
b) False
Answer: b
Clarification: There is no restriction on usage of any kind of statements while realizing a combinational circuit. Combinational circuit may be implemented by using statements like IF, CASE etc.

3. Which of the following is not a combinational circuit?
a) Adder
b) Code convertor
c) Multiplexer
d) Counter
Answer: d
Clarification: Since counter makes use of either clock signal or previous output to determine next state. Therefore, counter is a sequential circuit and all the others like multiplexer, adder and code convertors are the examples of combinational circuit.

4. The code given below is a VHDL implementation of _________

ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
         x1 WHEN “01”;
         x2 WHEN “10”;
         x3 WHEN “11”;
END my_circuit;

a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX
Answer: a
Clarification: In the given architecture, the output is single (y), which is selected with the help of a and b. So, a and b are select lines and y is the output which is selected from 4 inputs. Therefore, it is the multiplexer circuit with 4 inputs and 1 output.

5. Which of the following line of the code contains an error?

L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4:   <= x1 WHEN x = ‘1’;
L5: END mux1;

a) L2
b) L3
c) L4
d) No error
Answer: d
Clarification: There is no error in the given piece of the code. However, there was no need to use WHEN in the line L4 because there is no other case to be selected from many inputs. Last case can be directly expressed without any use of WHEN.

6. In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?
a) WITH-SELECT
b) WITH-SELECT-WHEN
c) IF-ELSE
d) CASE
Answer: b
Clarification: Because only concurrent statements can be used, therefore, WITH-SELECT is the correct alternative for the method used by the user. But, WITH-SELECT also requires WHEN keyword to implement the selected assignment.

7. Which of the following entity declares the ports of a 3 by 8 decoder?
a)

    ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
     END decoder;

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
     END decoder;

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
     END decoder;

     ENTITY decoder IS
     PORT( inp : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                 Outp: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
     END decoder;

View Answer

Answer: d
Clarification: In a 3 by 8 decoder, there must be 3 inputs and 8 outputs. For 3 inputs the dimension of vector must be 2 DOWNTO 0 and for output the dimensions should be 7 DOWNTO 0. Therefore, option d is the correct port entity of the 3 by 8 decoder.

8. For using a process to implement a combinational circuit, which signals should be in the sensitivity list?
a) Inputs of the circuit
b) Outputs of the circuit
c) Both of the Inputs and Outputs
d) No signal should be in the sensitivity list
Answer: a
Clarification: In a process used for the implementation of the combinational circuit, all the input signals used which are to be read, should appear in its sensitivity list. In a combinational circuit, there can be many inputs and those inputs should appear in the sensitivity list of the process.

9. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
a) Binary, Octal
b) Octal, Binary
c) Hexadecimal, Binary
d) Binary, Hexadecimal
Answer: c
Clarification: Since, 2⁴ = 16, therefore, the decoder can act as hexadecimal to binary converter. Because, 4 bits input is converted to 16 bits output. Each bit corresponding to 4 output bits. So, clearly it is a hexadecimal to binary convertor.

10. Following entity may represent a ________ circuit.

ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
              x    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
              y    : OUT STD_LOGIC);
END my_circuit;

a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adder
Answer: d
Clarification: The entity gives information about inputs and outputs of the circuit. The circuit has two inputs and both are of vector type. There is one vector output and another single bit output. Therefore, it has to be an adder, but because 4 bits are there in the input and output so it is a 4-bit parallel adder.