This set of VHDL Questions and Answers for Freshers on “Types of VHDL Modelling”.
1. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
Answer: b
Clarification: Modeling refers to the descriptive style we are using to describe our digital system. Modeling type is the type of statement used in architecture block to describe a specific system or circuit. It may define a structure or behavior or anything else.
2. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
Answer: d
Clarification: VHDL modeling is of three types. These types are behavioral modeling, dataflow modeling and structural modeling. There is no such modeling called component modeling. However, one can declare components in structural modeling.
3. In behavioral modeling, what do descriptive statements describe?
a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution
Answer: a
Clarification: Behavioral style specifies what a particular system does in a program. It gives the details of output values corresponding to the set of input values. In general, behavioral modeling use processes to describe the functioning of system, but no detail is provided regarding the design of the system.
4. Which of the following statement is used in structural modeling?
a) portmap()
b) process()
c) if-else
d) case
Answer: a
Clarification: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap() function is used to map the specific component in the design.
5. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow
Answer: c
Clarification: The primary unit of a behavior description in VHDL is process which describes the behavior of system on various combinations of inputs. All the system is described by using processes and therefore, process is the basic unit.
6. Which of the following modeling style follows the sequential processing of instructions?
a) Dataflow modeling
b) Behavior modeling
c) Structural modeling
d) Component modeling
Answer: b
Clarification: Behavior modeling uses sequential processing whereas dataflow and structural modeling uses concurrent statements. In sequential statements, the instructions are executed one after another whereas concurrent statements are executed simultaneously.
7. __________ modeling uses logic gates and basic blocks to describe the functionality of system.
a) Behavioral
b) Structural
c) Dataflow
d) Component
Answer: c
Clarification: In dataflow modeling, the system is represented as flow of control and movement of data. It describes how data flows from input to output by using primitive logic functions. Unlike behavioral modeling, it uses concurrent statements and logic functions.
8. Structural style use processes.
a) True
b) False
Answer: b
Clarification: Structural style does not use processes since it just describe the graphical representation of system. It doesn’t need process statements. Process statements are required to describe the behavior and not structure. Therefore, structural doesn’t need processes.
9. Component instantiation is the part of __________ modeling.
a) Behavior
b) Component
c) Dataflow
d) Structural
Answer: d
Clarification: Component declaration and component instantiation is a part of structural modeling. It first declares the component and then instantiation takes place by using portmap function. Structural modeling is based on netlist.
10. Which of the following architecture defines the data flow modeling of ‘and’ gate?
a)
ARCHITECTURE and_1 OF and_gate IS begin y <= a AND b; end and_1;
b)
ARCHITECTURE dataflow OF and_gate IS Process(a, b, y); begin y <= a AND b; end dataflow;
c)
ARCHITECTURE and_1 OF and_gate IS begin IF(a = ‘1’ and b = ‘1’) THEN c <= 1; ELSE c <= ‘0’; end and_1;
d)
ARCHITECTURE dataflow OF and_gate IS begin y <= a AND b; end and_1;
View Answer
Answer: a
Clarification: Dataflow uses primitive and basic functions to describe the flow of data through registers from inputs to output. It uses concurrent statements and process() is a sequential statement which can’t be used in data flow modeling. It is not necessary to write the name of ARCHITECTURE as ‘dataflow’.
11. Refer to the code given below, which type of modeling is used to describe the system?
ARCHITECTURE and_1 OF and_gate IS begin process(a, b, y) begin IF(a = ‘1’ and b = ‘1’) THEN y <= ‘1’; ELSE y <=’0’; end IF; END process; END and_1;
a) Structural
b) Component
c) Dataflow
d) Behavioral
Answer: d
Clarification: Above shown code is for AND gate and it is using process statement. The code gives information about output values for different combinations of input values. Therefore, the code given is behavioral style of modeling.
12. Which logic function is described in the code given below?
ARCHITECTURE my_func OF my_logic IS begin process(a, b, y) begin IF(a = ‘0’ and b = ‘0’) THEN y <= ‘0’; ELSIF (a = ‘1’ and b= ‘1’) THEN y<= ‘0’; ELSE y <= ‘1’; END if; END process; END my_func;
a) AND
b) EXOR
c) OR
d) EXNOR
Answer: b
Clarification: The modeling shown is behavioral modeling. The output y is low for 00 and 11 else the output is high. Therefore, the given logic is for exclusive OR gate. Since in EXOR he output is high for 01 and 10 which is shown in the code given.
13. Which modeling style does the following code represents?
Architecture my_logic OF logic_func IS Component gate_1 PORT (b1, b2 : IN BIT; s : OUT BIT); END component; Component gate_2 IS PORT (b1,b2 : IN BIT; C : OUT BIT); END component; SIGNAL a, b, sum, carry : BIT; begin EXOR : gate_1 portmap (a, b, sum); AND : gate_2 portmap (a,b ,carry); END my_logic
a) Structural
b) Component
c) Behavior
d) Dataflow
Answer: a
Clarification: The code describes the every component present in the circuit, here gate_1 and gate_2 are two components and then it describes the inputs and outputs of the gates by using portmap function. In this way structural modeling describes all the functions and their interconnection. Moreover, it uses concurrent statements.
14. Ports are known as _________ to the component.
a) Structure
b) Behavior
c) Function
d) Interface
Answer: d
Clarification: Ports are used to declare the inputs and outputs of a specific component in the structural modeling. They act as an external interface of the component since it tells the number of input and outputs a component can have.
15. What is the use of a function called port map()?
a) Component declaration
b) Defining identifiers
c) Component instantiation
d) Defining inputs and outputs
Answer: c
Clarification: The function portmap() is used for component instantiation. By taking instances of input output ports declared at the time of declaration, the component is instantiated. Basically, to define the relation of component with the signals, we use portmap().
VHDL for Freshers, .