Category: Digital Circuits Objective Questions

Digital Electronic/Circuits question bank on “Flip Flops – 3”.

1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
A. Gated JK-latch
B. Gated SR-latch
C. Gated T-latch
D. Gated D-latch
Answer: D
Clarification: Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the number of inputs.

2. The characteristic of J-K flip-flop is similar to _____________
A. S-R flip-flop
B. D flip-flop
C. T flip-flop
D. Gated T flip-flop
Answer: A
Clarification: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is shown by J-K flip-flop.

3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
A. Two AND gates
B. Two NAND gates
C. Two NOT gates
D. Two OR gates
Answer: A
Clarification: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.

4. How is a J-K flip-flop made to toggle?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: D
Clarification: When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is device is either set or reset.

5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________
A. Parity error checking
B. Ones catching
C. Digital discrimination
D. Digital filtering
Answer: B
Clarification: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

6. In J-K flip-flop, “no change” condition appears when ___________
A. J = 1, K = 1
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 0, K = 0
Answer: D
Clarification: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.

7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
A. Constantly LOW
B. Constantly HIGH
C. A 20 kHz square wave
D. A 10 kHz square wave
Answer: D
Clarification: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

8. What is the significance of the J and K terminals on the J-K flip-flop?
A. There is no known significance in their designations
B. The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
C. The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
D. All of the other letters of the alphabet are already in use
Answer: C
Clarification: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the toggling of states.

9. On a J-K flip-flop, when is the flip-flop in a hold condition?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
Answer: A
Clarification: At J=0 k=0 output continues to be in the same state. This is the memory storing state.

10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________
A. 00
B. 11
C. 01
D. 10
Answer: A
Clarification: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 2² = 4). So after 4 clock pulses the O/P repeats i.e. 00.

11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
A. 1 kHz
B. 2 kHz
C. 4 kHz
D. 16 kHz
Answer: B
Clarification: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop. Since the output frequency is determined on basis of the 4^th flip-flop.

12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz
Answer: B
Clarification: 12 flip flops = 2¹² = 4096
Input Clock frequency = 20.48*10⁶ = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

13. How many flip-flops are in the 7475 IC?
A. 2
B. 1
C. 4
D. 8
Answer: C
Clarification: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.

Digital Electronic Circuits question bank,

Digital Electronics/Circuits Multiple Choice Questions on “Ring Counter”.

1. Ring shift and Johnson counters are ____________
A. Synchronous counters
B. Asynchronous counters
C. True binary counters
D. Synchronous and true binary counters
Answer: A
Clarification: Synchronous counters are the counters being triggered in the presence of a clock pulse. Since all of the clock inputs are connected through a single clock pulse in ring shift and johnson counters. So, both are synchronous counters.

2. What is the difference between a shift-right register and a shift-left register?
A. There is no difference
B. The direction of the shift
C. Propagation delay
D. The clock input
Answer: B
Clarification: In shift-right register, shifting of bit takes place towards the right and towards left for shift-left register. Thus, both the registers vary in the shifting of their direction.

3. What is a transceiver circuit?
A. A buffer that transfers data from input to output
B. A buffer that transfers data from output to input
C. A buffer that can operate in both directions
D. A buffer that can operate in one direction
Answer: C
Clarification: A transceiver circuit is a buffer that can operate in both directions right as well as left.

4. A 74HC195 4-bit parallel access shift register can be used for ____________
A. Serial in/serial out operation
B. Serial in/parallel out operation
C. Parallel in/serial out operation
D. All of the Mentioned
Answer: D
Clarification: 74HC195 is an IC, which can be used for all of the given operations, as well as for, parallel-in/parallel-out.

5. Which type of device may be used to interface a parallel data format with external equipment’s serial format?
A. UART
B. Key matrix
C. Memory chip
D. Series in Parallel out
Answer: A
Clarification: UART means Universal Asynchronous Receiver/Transmitter which converts the bytes it receives from the computer along parallel circuits into a single serial bit stream for outbound transmission. And also receives data in serial form and converts it into parallel form and sent to the processor.

6. What is the function of a buffer circuit?
A. To provide an output that is inverted from that on the input
B. To provide an output that is equal to its input
C. To clean up the input
D. To clean up the output
Answer: B
Clarification: The function of a buffer circuit is to provide an output that is equal to its input. A transceiver circuit is a buffer that can operate in both directions right as well as left.

7. What is the preset condition for a ring shift counter?
A. All FFs set to 1
B. All FFs cleared to 0
C. A single 0, the rest 1
D. A single 1, the rest 0
Answer: D
Clarification: A ring shift counter is a counter in which the output of one FF connected to the input of the adjacent FF. In preset condition, all of the bits are 0 except first one.

8. Which is not characteristic of a shift register?
A. Serial in/parallel in
B. Serial in/parallel out
C. Parallel in/serial out
D. Parallel in/parallel out
Answer: A
Clarification: There is no such type of register present who doesn’t have output end. Thus, Serial in/Parallel in is not a characteristic of a shift register. There has to be an output, be it serial or parallel.

9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ____________
A. Divide-by-4 clock pulse
B. Sequence generator
C. Strobe line
D. Multiplexer
Answer: C
Clarification: In computer or memory technology, a strobe is a signal that is sent that validates data or other signals on adjacent parallel lines. Thus, in registers the strobe line is there to check the availability of data.

10. Another way to connect devices to a shared data bus is to use a ____________
A. Circulating gate
B. Transceiver
C. Bidirectional encoder
D. Strobed latch
Answer: B
Clarification: A transceiver is a device comprising both a transmitter and a receiver which are combined and share common circuitry or a single housing. When no circuitry is common between transmit and receive functions, the device is a transmitter-receiver.

Digital Electronics/Circuits Multiple Choice Questions on “Emitter-Coupled Logic(ECL)”.

1. The full form of ECL is __________
A. Emitter-collector logic
B. Emitter-complementary logic
C. Emitter-coupled logic
D. Emitter-cored logic
Answer: C
Clarification: The full form of ECL is emitter-coupled logic.

2. Which logic is the fastest of all the logic families?
A. TTL
B. ECL
C. HTL
D. DTL
Answer: B
Clarification: ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results in the highest transmission rate.

3. The full form of CML is __________
A. Complementary mode logic
B. Current mode logic
C. Collector mode logic
D. Collector Mixed Logic
Answer: C
Clarification: The full form of CML is Collector Mode Logic.

4. Sometimes ECL can also be named as __________
A. EEL
B. CEL
C. CML
D. CCL
Answer: C
Clarification: ECL (Emitter Coupled LogiC. can also be named as CML(Collector Mode LogiC..

5. In an ECL the output is taken from __________
A. Emitter
B. Base
C. Collector
D. Junction of emitter and base
Answer: C
Clarification: Though, the emitter and collector of the ECL are coupled together. So, the output will be taken from a collector.

6. The ECL behaves as __________
A. NOT gate
B. NOR gate
C. NAND gate
D. AND gate
Answer: B
Clarification: The ECL behaves as NOR gate because if any of the input voltages go high as compared to the reference voltage, the output is low and the output is high only when all the input voltages are low.

7. In ECL the fanout capability is __________
A. High
B. Low
C. Zero
D. Sometimes high and sometimes low
Answer: A
Clarification: If the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. Fan-out is the measure of the maximum number of inputs that a single gate output can accept.

8. ECL’s major disadvantage is that __________
A. It requires more power
B. It’s fanout capability is high
C. It creates more noise
D. It is slow
Answer: A
Clarification: ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families. But ECL logic gates have clock frequency. Thus, they have a fast operation.

9. The full form of SCFL is __________
A. Source-collector logic
B. Source-coupled logic
C. Source-complementary logic
D. Source Cored Logic
Answer: B
Clarification: The full form of SCFL is source-coupled logic.

10. The equivalent of emitter-coupled logic made out of FETs is called __________
A. CML
B. SCFL
C. FECL
D. EFCL
Answer: B
Clarification: The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL). Like ECL, SCL is also the fastest among the logic families.

11. ECL was invented in _______ by __________
A. 1956, Baker clamp
B. 1976, James R. Biard
C. 1956, Hannon S. Yourke
D. 1976, Yourke
Answer: C
Clarification: ECL was invented in August 1956 at IBM by Hannon S Yourke.

12. At the time of invention, an ECL was called as __________
A. Source-coupled logic
B. Current Mode Logic
C. Current-steering logic
D. Emitter-coupled logic
Answer: C
Clarification: At the time of invention, an ECL was called a current-steering logic because it involved current switching.

13. The ECL circuits usually operates with __________
A. Negative voltage
B. Positive voltage
C. Grounded voltage
D. High Voltage
Answer: A
Clarification: The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to grounD., in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.

14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of __________
A. ECL
B. VECL
C. PECL
D. LECL
Answer: C
Clarification: Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V instead of 5 V supply.

Digital Electronics/Circuits Multiple Choice Questions on “BCD Adder”.

1. The decimal number system represents the decimal number in the form of ____________
A. Hexadecimal
B. Binary coded
C. Octal
D. Decimal
Answer: B
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Hexadecimal and Octal are number systems having base 16 and 8 respectively.

2. 2⁹ input circuit will have total of ____________
A. 32 entries
B. 128 entries
C. 256 entries
D. 512 entries
Answer: D
Clarification: 2⁹ input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

3. BCD adder can be constructed with 3 IC packages each of ____________
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Answer: C
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration) package.

4. The output sum of two decimal digits can be represented in ____________
A. Gray Code
B. Excess-3
C. BCD
D. Hexadecimal
Answer: C
Clarification: The output sum of two decimal digits can be represented in BCD(Binary-coded decimal). Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight.

5. The addition of two decimal digits in BCD can be done through ____________
A. BCD adder
B. Full adder
C. Ripple carry adder
D. Carry look ahead
Answer: A
Clarification: The addition of two decimal digits in BCD can be done through BCD adder. Every input inserted, in addition by the user converted into binary and then proceed for the addition. Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary bits.

6. 3 bits full adder contains ____________
A. 3 combinational inputs
B. 4 combinational inputs
C. 6 combinational inputs
D. 8 combinational inputs
Answer: D
Clarification: 3 bits full adder contains 2³ = 8 combinational inputs.

7. The simplified expression of full adder carry is ____________
A. c = xy+xz+yz
B. c = xy+xz
C. c = xy+yz
D. c = x+y+z
Answer: A
Clarification: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.

8. Complement of F’ gives back __________
A. F’
B. F
C. FF
D. FF’
Answer: B
Clarification: Complement means inversion. So, complement of F’ gives back F, as per the Law of Involution.

9. Decimal digit in BCD can be represented by ____________
A. 1 input line
B. 2 input lines
C. 3 input lines
D. 4 input lines
Answer: D
Clarification: Binary-coded decimal (BCD. is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.

10. The number of logic gates and the way of their interconnections can be classified as ____________
A. Logical network
B. System network
C. Circuit network
D. Gate network
Answer: A
Clarification: The number of different levels of logic gates is represented in a fashion which is known as a logical network.

Digital Electronics/Circuits Multiple Choice Questions on “D Flip Flop”.

1. In D flip-flop, D stands for _____________
A. Distant
B. Data
C. Desired
D. Delay
Answer: B
Clarification: The D of D-flip-flop stands for “data”. It stores the value on the data line.

2. The D flip-flop has _______ input.
A. 1
B. 2
C. 3
D. 4
Answer: A
Clarification: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

3. The D flip-flop has ______ output/outputs.
A. 2
B. 3
C. 4
D. 1
Answer: A
Clarification: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

4. A D flip-flop can be constructed from an ______ flip-flop.
A. S-R
B. J-K
C. T
D. S-K
Answer: A
Clarification: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.

5. In D flip-flop, if clock input is LOW, the D input ___________
A. Has no effect
B. Goes high
C. Goes low
D. Has effect
Answer: A
Clarification: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.

6. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
A. 0
B. 1
C. Forbidden
D. Toggle
Answer: A
Clarification: If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram: