250+ TOP MCQs on Logic Gates and Networks – 1 and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Logic Gates and Networks – 1”.

1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	0

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	1

The gate is either _________
A. A NAND or an EX-OR
B. An OR or an EX-NOR
C. An AND or an EX-OR
D. A NOR or an EX-NOR
Answer: D
Clarification: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in the above table).

2. The code where all successive numbers differ from their preceding number by single bit is __________
A. Alphanumeric Code
B. BCD
C. Excess 3
D. Gray
Answer: D
Clarification: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.

3. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
A. 2 to 4 line
B. 3 to 8 line
C. 4 to 16 line
D. 5 to 32 line
Answer: C
Clarification: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

4. How many AND gates are required to realize Y = CD + EF + G?
A. 4
B. 5
C. 3
D. 2
Answer: D
Clarification: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

5. The NOR gate output will be high if the two inputs are __________
A. 00
B. 01
C. 10
D. 11
Answer: A
Clarification: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
A. 2, 2
B. 2, 3
C. 3, 3
D. 3, 2
Answer: A
Clarification: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

7. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
A. OR
B. AND
C. XOR
D. NAND
Answer: D
Clarification: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.

8. A full adder logic circuit will have __________
A. Two inputs and one output
B. Three inputs and three outputs
C. Two inputs and two outputs
D. Three inputs and two outputs
Answer: D
Clarification: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
A. 3, 2
B. 4, 2
C. 1, 1
D. 2, 3
Answer: A
Clarification: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

10. Which of the following are known as universal gates?
A. NAND & NOR
B. AND & OR
C. XOR & OR
D. EX-NOR & XOR
Answer: A
Clarification: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.

11. The gates required to build a half adder are __________
A. EX-OR gate and NOR gate
B. EX-OR gate and OR gate
C. EX-OR gate and AND gate
D. EX-NOR gate and AND gate
Answer: C
Clarification: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.