Category: Digital Circuits Objective Questions

250+ TOP MCQs on Diode-Transistor Logic(DTL) and Answers

his set of Digital Electronics/Circuits Multiple Choice Questions on “Diode-Transistor Logic(DTL)”.

1. Diode–transistor logic (DTL) is the direct ancestor of _____________
A. Register-transistor logic
B. Transistor–transistor logic
C. High threshold logic
D. Emitter Coupled Logic
Answer: B
Clarification: Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic. To overcome the shortcomings of DTL, TTL came into existence.

2. In DTL logic gating function is performed by ___________
A. Diode
B. Transistor
C. Inductor
D. Capacitor
Answer: A
Clarification: Diode serves as the input network and the switching operation is performed by the transistor.

3. In DTL amplifying function is performed by ___________
A. Diode
B. Transistor
C. Inductor
D. Capacitor
Answer: B
Clarification: The amplifying and switching function is performed by a transistor and the diode acts an input network in DTL.

4. How many stages a DTL consist of?
A. 2
B. 3
C. 4
D. 5
Answer: B
Clarification: The DTL circuit shown in the picture consists of three stages: an input diode logic stage, an intermediate level shifting stage and an output common-emitter amplifier stage.

5. The full form of CTDL is ___________
A. Complemented transistor diode logic
B. Complemented transistor direct logic
C. Complementary transistor diode logic
D. Complementary transistor direct logic
Answer: A
Clarification: The full form of CTDL is Complemented transistor diode logic.

6. The DTL propagation delay is relatively ___________
A. Large
B. Small
C. Moderate
D. Negligible
Answer: A
Clarification: Propagation delay refers to the time taken by the output to change it’s state when the input is altered. When the transistor goes into saturation from all inputs being high charge is stored in the base region. When it comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time which results as a large propagation delay. Thus, it has small clock frequency.

7. The way to speed up DTL is to add an across intermediate resister is ___________
A. Small “speed-up” capacitor
B. Large “speed-up” capacitor
C. Small “speed-up” transistor
D. Large ” speed-up” transistor
Answer: A
Clarification: One way to speed up DTL is to add a small “speed-up” capacitor across intermediate resister. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the transistor by increasing the initial base drive.

8. The process to avoid saturating the switching transistor is performed by ___________
A. Baker clamp
B. James R. Biard
C. Chris Brown
D. Totem-Pole
Answer: A
Clarification: Another way to speed up DTL other than adding a small “speed-up” capacitor across intermediate resister is to avoid saturating the switching transistor which can be done with a Baker clamp. The name Baker clamp is given at the name of Richard H. Baker, who described it in his 1956 technical report “Maximum Efficiency Switching Circuits”.

9. A major advantage of DTL over the earlier resistor–transistor logic is the ___________
A. Increased fan out
B. Increased fan in
C. Decreased fan out
D. Decreased fan in
Answer: B
Clarification: A major advantage over the earlier resistor–transistor logic is the increased fan in. Fan-in is the measure of the maximum number of inputs that a single gate output can accept.

10. To increase fan-out of the gate in DTL ___________
A. An additional capacitor may be used
B. An additional resister may be used
C. An additional transistor and diode may be used
D. Only an additional diode may be used
Answer: C
Clarification: To increase fan-out of the gate in DTL, an additional transistor and diode may be used. Here, the fan out means the number of maximum input that a single gate output can feed.

11. A disadvantage of DTL is ___________
A. The input transistor to the resister
B. The input resister to the transistor
C. The increased fan-in
D. The increased fan-out
Answer: B
Clarification: A disadvantage of DTL is the input resistor to the transistor and its presence tends to slow the circuit down. Hence limiting the speed at which the transistor is able to switch states. Thus, the propagation delay increases.

250+ TOP MCQs on Fast Adder & Serial Adder – 1 and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Fast Adder & Serial Adder – 1”.

1. The inverter can be produced with how many NAND gates?
A. 2
B. 1
C. 3
D. 4
Answer: B
Clarification: The inverter can be produced with the help of single NAND gate, because we can send a single input twice through the same NAND gate together, thus producing the inverted version of the input as output. It works as an inverter.

2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output’s relation with the inputs?
A. The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses
B. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses
C. The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
D. The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
Answer: D
Clarification: When both the input pulses are high or low X-OR output is low. But when one of the input is high and another is low or vice-versa, output is high. In this problem for the first 20uS one input is high and another is low. So, obviously output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15) first input is still high and second one is low so output is high.

3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: Since in the given expression two inputs are complemented. So, we require two NOT gate at the input. A NOT gate is a basic gate which accepts a single input and produces a single output, which is the inverted version of the input.

4. The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and ________ if a high order carry is generated.
A. Addend, minuend
B. Minuend, subtrahend
C. Addend, minuend
D. Augend, addend
Answer: D
Clarification: The carry look ahead adder is based on the principle of looking at the lower order bits of the augend and addend if a high order carry is generated. A carry look ahead adder is a type of adder which reduces the propagation delay.

5. What are carry generate combinations?
A. If all the input are same then a carry is generated
B. If all of the output are independent of the inputs
C. If all of the input are dependent on the output
D. If all of the output are dependent on the input
Answer: B
Clarification: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate combinations.

6. In serial addition, the addition is carried out __________
A. 3 bit per second
B. Byte by byte
C. Bit by bit
D. All bits at the same time
Answer: C
Clarification: In serial addition, the addition is carried out bit by bit.

7. How many shift registers are used in a 4 bit serial adder?
A. 4
B. 3
C. 2
D. 5
Answer: C
Clarification: There are two shift registers are used in a 4-bit serial adder, which is used to store the numbers to be added serially. Serial addition takes place bit by bit.

8. A D flip-flop is used in a 4-bit serial adder, why?
A. It is used to invert the input of the full adder
B. It is used to store the output of the full adder
C. It is used to store the carry output of the full adder
D. It is used to store the sum output of the full adder
Answer: C
Clarification: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be added to the next significant position of the numbers in the registers.

9. What is ripple carry adder?
A. The carry output of the lower order stage is connected to the carry input of the next higher order stage
B. The carry input of the lower order stage is connected to the carry output of the next higher order stage
C. The carry output of the higher order stage is connected to the carry input of the next lower order stage
D. The carry input of the higher order stage is connected to the carry output of the lower order stage
Answer: A
Clarification: When the carry output of the lower order stage is connected to the carry input of the next higher order stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.

10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be __________
A. 0
B. 1
C. Floating
D. High Impedance
Answer: B
Clarification: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step (i.e 0 – 1 – 1 = 0, borrow = 1).

250+ TOP MCQs on Flip Flops – 2 and Answers

Digital Electronic/Circuits online quiz on “Flip Flops”.

1. What is an ambiguous condition in a NAND based S’-R’ latch?
A. S’=0, R’=1
B. S’=1, R’=0
C. S’=1, R’=1
D. S’=0, R’=0

Answer: D
Clarification: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called an ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.

2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
A. No change
B. Set
C. Reset
D. Forbidden

Answer: A
Clarification: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the state. It remains in its prior state. This state is used for the storage of data.

3. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
A. A D latch at each of its input
B. An inverter at each of its input
C. It can never be converted
D. Both a D latch and an inverter at its input

Answer: D
Clarification: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an inverter at its input as it’s operations will be complementary.

4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
A. The inputs of NOR latch are 0 but 1 for NAND latch
B. The inputs of NOR latch are 1 but 0 for NAND latch
C. The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
D. The output of NOR latch is 1 but 0 for NAND latch

Answer: A
Clarification: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.

5. The characteristic equation of S-R latch is ____________
A. Q(n+1) = (S + Q(n))R’
B. Q(n+1) = SR + Q(n)R
C. Q(n+1) = S’R + Q(n)R
D. Q(n+1) = S’R + Q'(n)R

Answer: A
Clarification: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.

6. The difference between a flip-flop & latch is ____________
A. Both are same
B. Flip-flop consist of an extra output
C. Latches has one input but flip-flop has two
D. Latch has two inputs but flip-flop has one

Answer: C
Clarification: Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is provided to the latch.

7. How many types of flip-flops are?
A. 2
B. 3
C. 4
D. 5

Answer: C
Clarification: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

8. The S-R flip flop consist of ____________
A. 4 AND gates
B. Two additional AND gates
C. An additional clock input
D. 3 AND gates

Answer: B
Clarification: The S-R flip flop consists of two additional AND gates at the S and R inputs of S-R latch.

9. What is one disadvantage of an S-R flip-flop?
A. It has no Enable input
B. It has a RACE condition
C. It has no clock input
D. Invalid State

Answer: D
Clarification: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State.

10. One example of the use of an S-R flip-flop is as ____________
A. Racer
B. Stable oscillator
C. Binary storage register
D. Transition pulse generator

Answer: C
Clarification: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary storage element. It functions as memory storage during the No Change State.

11. When is a flip-flop said to be transparent?
A. When the Q output is opposite the input
B. When the Q output follows the input
C. When you can see through the IC packaging
D. When the Q output is complementary of the input

Answer: B
Clarification: Flip-flop have the property of responding immediately to the changes in its inputs. This property is called transparency.

12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
A. The clock pulse is LOW
B. The clock pulse is HIGH
C. The clock pulse transitions from LOW to HIGH
D. The clock pulse transitions from HIGH to LOW

Answer: C
Clarification: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.

13. What is the hold condition of a flip-flop?
A. Both S and R inputs activated
B. No active S or R input
C. Only S is active
D. Only R is active

Answer: B
Clarification: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No Change State or Memory Storage state if a flip-flop.

14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________
A. SET
B. RESET
C. Clear
D. Invalid

Answer: B
Clarification: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.

15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________
A. Edge-detection circuit
B. NOR latch
C. NAND latch
D. Pulse-steering circuit

Answer: A
Clarification: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the edge-detection circuit.

250+ TOP MCQs on Shift Register Counters and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Shift Register Counters”.

1. What is a recirculating register?
A. Serial out connected to serial in
B. All Q outputs connected together
C. A register that can be used over again
D. Parallel out connected to Parallel in
Answer: A
Clarification: A recirculating register is a register whose serial output is connected to the serial input in a circulated manner.

2. When is it important to use a three-state buffer?
A. When two or more outputs are connected to the same input
B. When all outputs are normally HIGH
C. When all outputs are normally LOW
D. When two or more outputs are connected to two or more inputs
Answer: A
Clarification: When two or more outputs are connected to the same input, in such situation we use of tristate buffer always because it has the capability to take upto three inputs. A buffer is a circuit where the output follows the input.

3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________
A. 1110
B. 0111
C. 1000
D. 1001
Answer: D
Clarification: Given,

Stored nibble | waiting nibble
         0111 | 1110, Initially  
          111 | 1100, 1st pulse
           11 | 1001, 2nd pulse.

4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________
A. 1110
B. 0001
C. 1100
D. 1000
Answer: B
Clarification: Parallel in parallel out gives the same output as input. Thus, after three clock pulses, the data outputs are 0001.

5. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ______________
A. 10111000
B. 10110111
C. 11110000
D. 11111100
Answer: D
Clarification: After first clock pulse, the register contains 11111000. After second clock pulse, the register would contain 11111100. Since the bits are shifted to the right at every clock pulse.

6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a ________ ________ and ________ out register.
A. Parallel-in, serial, parallel
B. Serial-in, parallel, serial
C. Series-parallel-in, series, parallel
D. Bidirectional in, parallel, series
Answer: A
Clarification: One bit shifting takes place just after the output obtained on every register. Hence, by adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-in, Serial, and Parallel-out register. Since, the bots can be inputted all at the same time, while the data can be outputted either one at a time or simultaneously.

7. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?
A. Parallel-in Parallel-out
B. Parallel-in Serial-out
C. Serial-in Serial-out
D. Serial-in Parallel-out
Answer: C
Clarification: Serial-in Serial-out register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time. Since in serial transmission, bits are transmitted or received one at a time and not simultaneously.

8. In a 4-bit Johnson counter sequence, there are a total of how many states or bit patterns?
A. 1
B. 3
C. 4
D. 8
Answer: D
Clarification: In johnson counter, total number of states are determined by 2N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8
Total Number of Unused states = 16 – 8 = 8.

9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
A. 1101000000
B. 0011010000
C. 1100000000
D. 0000000000
Answer: B
Clarification: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at 1st position and 2nd position which came from the last two bits). As in a ring counter, the bits rotate in clockwise direction.

10. How much storage capacity does each stage in a shift register represent?
A. One bit
B. Two bits
C. Four bits
D. Eight bits
Answer: A
Clarification: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a shift register has the capability to store one bit and if another bit is to store, in such a situation it deletes the previous data and stores them.

250+ TOP MCQs on Random Access Memory – 4 and Answers

Basic Digital Electronic/Circuits Interview questions and answers on “Random Access Memory-4”.

1. DRAM is fabricated by using IC __________
A. 2114
B. 7489
C. 4116
D. 2776
Answer: C
Clarification: DRAM is Dynamic RAM which takes more access time compared to SRAM and is thus, slower in operation comparatively. Although, in general it offers high speed and is used in most computers nowadays. DRAM is fabricated by using IC 4116.

2. IC 4116 is of ______ storage memory.
A. 16 KB
B. 32 KB
C. 64 MB
D. 2 KB
Answer: A
Clarification: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V, and +12V) to operate the IC unit.

3. How many supply voltage IC 4116 requires to operate the IC unit?
A. 3
B. 2
C. 1
D. 4
Answer: A
Clarification: IC 4116 is a DRAM of 16 KB storage memory. It requires three supply voltages (+5V, -5V, and +12V) to operate the IC unit.

4. The full form of PSRAM is __________
A. Plugged Static RAM
B. Plugged Stored RAM
C. Pseudo Stored RAM
D. Pseudo Static RAM
Answer: D
Clarification: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM which is implemented as a SRAM.

5. Pseudo static RAM is a __________
A. Static RAM
B. Dynamic RAM
C. Cache
D. ROM
Answer: B
Clarification: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic, which is implemented as an SRAM.

6. When PSRAM is performing internal refresh __________
A. The read operation is performed
B. The write operation is performed
C. It can not be accessed for read or write
D. The voltage goes HIGH
Answer: C
Clarification: The full form of PSRAM is Pseudo Static RAM. It is a dynamic RAM having built-in fresh logic, which is implemented as a SRAM. So, it can not be accessed for read or write during the refresh operation.

7. RAMs are utilized in the computer as __________
A. Scratch-pad
B. Buffer
C. Main memory
D. All of the Mentioned
Answer: D
Clarification: RAMs are utilized in the computer as a scratch-pad, buffer and main memories. These are the applications of RAMs. Mostly, these RAMs are DRAMs as they provide high speed.

8. The advantages of RAMs are __________
A. Non destructive read out
B. Fast operating speed
C. Low power dissipation
D. All of the Mentioned
Answer: D
Clarification: The advantages of RAM are Non-destructive read out, Fast operating speed and Low power dissipation.

9. Which one is more economical?
A. ROM
B. RAM
C. EROM
D. PROM
Answer: B
Clarification: RAM is more economical than ROM because MOS memories are more economical than the magnetic core for small and medium sized systems.

10. Which one is self-compatible?
A. ROM
B. RAM
C. EROM
D. PROM
Answer: B
Clarification: As semiconductor memories enjoy common interface and technology between sensing and decoding circuitry and the storage element itself, so RAMs are self-compatible. Also, they provide high speed and fast operation.

11. The memory which is used for storing programs and data currently being processed by the CPU is called __________
A. PROM
B. Main Memory
C. Non-volatile memory
D. Mass memory
Answer: A
Clarification: PROM has the capability to store the data due to the presence of MOSFET which is processed by the CPU. It is one-time programmable by the user.

12. CD-ROM is a __________
A. Memory register
B. Magnetic memory
C. Semiconductor memory
D. Non-volatile memory
Answer: D
Clarification: CD-ROM is a non-volatile memory. Once a program is uploaded in it then it can’t be erasable. Thus, it stores the data permanently.

13. A place which is used as storage location in a computer __________
A. A bit
B. A record
C. An address
D. A byte
Answer: C
Clarification: A storage location of a computer is an address/memory location, used to store instructions and data.

14. Which of the following is not a primary storage device?
A. Optical disk
B. Magnetic tape
C. Magnetic disk
D. RAM
Answer: D
Clarification: RAM (i.e. Random Access Memory) is not a primary storage device.

basic questions on all areas of Digital Electronic Circuits,

250+ TOP MCQs on Number System and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Number System”.

1. The given hexadecimal number (1E.53)16 is equivalent to ____________
A. (35.684)8
B. (36.246)8
C. (34.340)8
D. (35.599)8

Answer: B
Clarification: First, the hexadecimal number is converted to it’s equivalent binary form, by writing the binary equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are grouped in terms of 3 bits and then for each of the 3-bits, the respective digit is written. Thus, the octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8.

2. The octal number (651.124)8 is equivalent to ______
A. (1A9.2A.16
B. (1B0.10)16
C. (1A8.A3)16
D. (1B0.B0)16

Answer: A
Clarification: First, the octal number is converted to it’s equivalent binary form, by writing the binary equivalent of each digit in form of 3 bits. Then, the binary equivalent bits are grouped in terms of 4 bits and then for each of the 4-bits, the respective digit is written. Thus, the hexadecimal equivalent is obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A.16.

3. The octal equivalent of the decimal number (417)10 is _____
A. (641)8
B. (619)8
C. (640)8
D. (598)8

Answer: A
Clarification: Octal equivalent of decimal number is obtained by dividing the number by 8 and collecting the remainders in reverse order.
8 | 417
8 | 52 — 1
8 | 6 – 4
So, (417)10 = (641)8.

4. Convert the hexadecimal number (1E2)16 to decimal.
A. 480
B. 483
C. 482
D. 484

Answer: C
Clarification: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of base index along with the value at that index position.
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)
= 256 + 224 + 2 = (482)10.

5. (170)10 is equivalent to ____________
A. (FD.16
B. (DF)16
C. (AA.16
D. (AF)16

Answer: C
Clarification: Hexadecimal equivalent of decimal number is obtained by dividing the number by 16 and collecting the remainders in reverse order.
16 | 170
16 | 10 – 10
Hence, (170)10 = (AA.16.

6. Convert (214)8 into decimal.
A. (140)10
B. (141)10
C. (142)10
D. (130)10

Answer: A
Clarification: Octal to Decimal conversion is obtained by multiplying 8 to the power of base index along with the value at that index position.
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10.

7. Convert (0.345)10 into an octal number.
A. (0.16050)8
B. (0.26050)8
C. (0.19450)8
D. (0.24040)8

Answer: B
Clarification: Converting decimal fraction into octal number is achieved by multiplying the fraction part by 8 everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8.

8. Convert the binary number (01011.1011)2 into decimal.
A. (11.6875)10
B. (11.5874)10
C. (10.9876)10
D. (10.7893)10

Answer: A
Clarification: Binary to Decimal conversion is obtained by multiplying 2 to the power of base index along with the value at that index position.
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10.

9. Octal to binary conversion: (24)8 =?
A. (111101)2
B. (010100)2
C. (111100)2
D. (101010)2

Answer: B
Clarification: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the binary equivalent of the octal number is obtained.
(24)8 = (010100)2.

10. Convert binary to octal: (110110001010)2 =?
A. (5512)8
B. (6612)8
C. (4532)8
D. (6745)8

Answer: B
Clarification: The binary equivalent is segregated into groups of 3 bits, starting from left. And then for each group, the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8.