250+ TOP MCQs on Quine McCluskey or Tabular Method of Minimization of Logic Functions and Answers

Digital Electronic Circuits Questions and Answers for freshers on “Quine-McCluskey or Tabular Method of Minimization of Logic Functions”.

1. The output of an EX-NOR gate is 1. Which input combination is correct?
A. A = 1, B = 0
B. A = 0, B = 1
C. A = 0, B = 0
D. A = 0, B’ = 1
Answer: C
Clarification: The output of EX-NOR gate is given by AB + A’B’. So, for A = 0 and B = 0 the output will be 1.

2. In which of the following gates the output is 1 if and only if at least one input is 1?
A. AND
B. NOR
C. NAND
D. OR
Answer: D
Clarification: In or gate we need at least one bit to be equal to 1 to generate the output as 1 because OR means any of the condition out of two is equal to 1 which means if at least one input is 1 then it shows output as 1.

3. The time required for a gate or inverter to change its state is called __________
A. Rise time
B. Decay time
C. Propagation time
D. Charging time
Answer: C
Clarification: The time required for a gate or inverter to change its state is called propagation time.

4. What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
A. One
B. Two
C. Three
D. Four
Answer: C
Clarification: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also write,
1st, 2nd and 3rd NAND operations as: Y = ((NOT A. AND (NOT B.)’ = A’’ + B’’ = (A+B..

5. Odd parity of word can be conveniently tested by ___________
A. OR gate
B. AND gate
C. NAND gate
D. XOR gate
Answer: D
Clarification: Odd parity of word can be conveniently tested by XOR gate, since, XOR outputs 1 only when the input has odd number of 1’s.

6. The number of full and half adders are required to add 16-bit number is __________
A. 8 half adders, 8 full adders
B. 1 half adders, 15 full adders
C. 16 half adders, 0 full adders
D. 4 half adders, 12 full adders
Answer: B
Clarification: Half adder has two inputs and two outputs whereas Full Adder has 3 inputs and 2 outputs. One half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries.

7. Which of the following will give the sum of full adders as output?
A. Three point major circuit
B. Three bit parity checker
C. Three bit comparator
D. Three bit counter
Answer: D
Clarification: Counters are used for counting purposes in ascending or descending order. Three bit counter will give the sum of full adders as output.

8. Which of the following gate is known as coincidence detector?
A. AND gate
B. OR gate
C. NOR gate
D. NAND gate
Answer: A
Clarification: AND gate is known as coincidence detector due to multiplicity behaviour, as it outputs 1 only when all the inputs are 1.

9. An OR gate can be imagined as ____________
A. Switches connected in series
B. Switches connected in parallel
C. MOS transistor connected in series
D. BJT transistor connected in series
Answer: B
Clarification: OR gate means addition of two inputs, which outputs when any of the input is high. Due to this reason, it is imagined as switches connected in parallel.

10. How many full adders are required to construct an m-bit parallel adder?
A. m/2
B. m
C. m-1
D. m+1
Answer: C
Clarification: We need adder for every bit. So we should need m bit adders. A full adder adds a carry bit to two inputs and produces an output and a carry. But the most significant bits can use a half adder which differs from the full adder as in that it has no carry input, so we need m-1 full adders and 1 half adder in m bit parallel adder.

for Freshers,