300+ REAL TIME Digital Circuits Objective Questions & Answers 2023

250+ TOP MCQs on Half Adder & Full Adder and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Half Adder & Full Adder”.

1. In parts of the processor, adders are used to calculate ____________
A. Addresses
B. Table indices
C. Increment and decrement operators
D. All of the Mentioned

Answer: D
Clarification: Adders are used to perform the operation of addition. Thus, in parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.

2. Total number of inputs in a half adder is __________
A. 2
B. 3
C. 4
D. 1

Answer: A
Clarification: Total number of inputs in a half adder is two. Since an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

3. In which operation carry is obtained?
A. Subtraction
B. Addition
C. Multiplication
D. Both addition and subtraction

Answer: B
Clarification: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 – 1 = 1 (borrow 1).

4. If A and B are the inputs of a half adder, the sum is given by __________
A. A AND B
B. A OR B
C. A XOR B
D. A EX-NOR B

Answer: C
Clarification: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry is given by A AND B.

5. If A and B are the inputs of a half adder, the carry is given by __________
A. A AND B
B. A OR B
C. A XOR B
D. A EX-NOR B

Answer: A
Clarification: If A and B are the inputs of a half adder, the carry is given by: A(AND.B, while the sum is given by A XOR B.

6. Half-adders have a major limitation in that they cannot __________
A. Accept a carry bit from a present stage
B. Accept a carry bit from a next stage
C. Accept a carry bit from a previous stage
D. Accept a carry bit from the following stages

Answer: C
Clarification: Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

7. The difference between half adder and full adder is __________
A. Half adder has two inputs while full adder has four inputs
B. Half adder has one output while full adder has two outputs
C. Half adder has two inputs while full adder has three inputs
D. All of the Mentioned

Answer: C
Clarification: Half adder has two inputs while full adder has three outputs; this is the difference between them, while both have two outputs SUM and CARRY.

8. If A, B and C are the inputs of a full adder then the sum is given by __________
A. A AND B AND C
B. A OR B AND C
C. A XOR B XOR C
D. A OR B OR C

Answer: C
Clarification: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR C.

9. If A, B and C are the inputs of a full adder then the carry is given by __________
A. A AND B OR (A OR B. AND C
B. A OR B OR (A AND B. C
C. (A AND B. OR (A AND B.C
D. A XOR B XOR (A XOR B. AND C

Answer: A
Clarification: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B. AND C, which is equivalent to (A AND B. OR (B AND C. OR (C AND A..

10. How many AND, OR and EXOR gates are required for the configuration of full adder?
A. 1, 2, 2
B. 2, 1, 2
C. 3, 1, 2
D. 4, 0, 1

Answer: B
Clarification: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2 EXOR.

250+ TOP MCQs on Encoders and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Encoders”.

1. How many inputs will a decimal-to-BCD encoder have?
A. 4
B. 8
C. 10
D. 16
Answer: C
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. Thus, a Decimal-to-bcd converter has decimal values as inputs which range from 0-9. So, a total of 10 inputs are there in a decimal-to-BCD encoder.

2. How many outputs will a decimal-to-BCD encoder have?
A. 4
B. 8
C. 12
D. 16
Answer: A
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. Thus, a decimal to BCD encoder has 4 outputs.

3. How is an encoder different from a decoder?
A. The output of an encoder is a binary code for 1-of-N input
B. The output of a decoder is a binary code for 1-of-N input
C. The output of an encoder is a binary code for N-of-1 output
D. The output of a decoder is a binary code for N-of-1 output
Answer: A
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. It performs the opposite operation of a decoder which results in 2ⁿ outputs from n inputs. Thus, an encoder different from a decoder because of the output of an encoder is a binary code for 1-of-N input.

4. If we record any music in any recorder, such types of process is called ___________
A. Multiplexing
B. Encoding
C. Decoding
D. Demultiplexing
Answer: B
Clarification: If we record any music in any recorder, it means that we are giving data to a recorder. So, such process is called encoding. Getting back the music from the recorded data is known as decoding.

5. Can an encoder be a transducer?
A. Yes
B. No
C. May or may not be
D. Both are not even related slightly
Answer: A
Clarification: Of course, a transducer is a device that has the capability to emit data as well as to accept. Transducer converts signal from one form of energy to another.

6. How many OR gates are required for a Decimal-to-bcd encoder?
A. 2
B. 10
C. 3
D. 4
Answer: D
Clarification: An encoder is a combinational circuit encoding the information of 2^n input lines to n output lines, thus producing the binary equivalent of the input.
This is clear from the diagram that it requires 4 OR gates:
.

7. How many OR gates are required for an octal-to-binary encoder?
A. 3
B. 2
C. 8
D. 10
Answer: A
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. Thus, in octal to binary encoder there are 8 (=2³) inputs, thus 3 output lines.

8. For 8-bit input encoder how many combinations are possible?
A. 8
B. 2^8
C. 4
D. 2^4
Answer: B
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. There are 2⁸ combinations are possible for an 8-bit input encoder but out of which only 8 are used using 3 output lines. It is a disadvantage of encoder.

9. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as ___________
A. Enable
B. Disable
C. Strobe
D. Clock
Answer: A
Clarification: Such problems are resolved by using enable input, which behaves as active if it gets 0 as input since it is an active-low pin.

10. Can an encoder be called a multiplexer?
A. No
B. Yes
C. Sometimes
D. Never
Answer: B
Clarification: A multiplexer or MUX is a combination circuit that contains more than one input line, one output line and more than one selection line. Whereas, an encoder is also considered a type of multiplexer but without a single output line and without any selection lines.

11. If two inputs are active on a priority encoder, which will be coded on the output?
A. The higher value
B. The lower value
C. Neither of the inputs
D. Both of the inputs
Answer: A
Clarification: An encoder is a combinational circuit encoding the information of 2ⁿ input lines to n output lines, thus producing the binary equivalent of the input. If two inputs are active on a priority encoder, the input of higher value will be coded in the output.

250+ TOP MCQs on Asynchronous Down Counter and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Asynchronous Down Counter”.

1. Which of the following statements are true?
A. Asynchronous events does not occur at the same time
B. Asynchronous events are controlled by a clock
C. Synchronous events does not need a clock to control them
D. Only asynchronous events need a control clock
Answer: A
Clarification: Asynchronous events does not occur at the same time because of propagation delay and they do need a clock pulse to trigger them. Whereas, synchronous events occur in presence of clock pulse.

2. A down counter using n-flip-flops count ______________
A. Downward from a maximum count
B. Upward from a minimum count
C. Downward from a minimum to maximum count
D. Toggles between Up and Down count
Answer: A
Clarification: As the name suggests down counter means counting occurs from a higher value to lower value (i.e. (2^n – 1) to 0).

3. UP Counter is ____________
A. It counts in upward manner
B. It count in down ward manner
C. It counts in both the direction
D. Toggles between Up and Down count
Answer: A
Clarification: UP counter counts in an upward manner from 0 to (2ⁿ – 1).

4. DOWN counter is ____________
A. It counts in upward manner
B. It count in downward manner
C. It counts in both the direction
D. Toggles between Up and Down count
Answer: B
Clarification: DOWN counter counts in a downward manner from (2ⁿ – 1) to 0.

5. How many different states does a 3-bit asynchronous down counter have?
A. 2
B. 4
C. 6
D. 8
Answer: D
Clarification: In a n-bit counter, the total number of states = 2ⁿ.
Therefore, in a 3-bit counter, the total number of states = 2³ = 8 states.

6. In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop goes from HIGH to LOW.
A. MSB flip-flop
B. LSB flip-flop
C. Master slave flip-flop
D. Latch
Answer: B
Clarification: Since the LSB flip-flop changes its state at each negative transition of clock. That is why LSB flip-flop doesn’t have toggle.

7. In a 3-bit asynchronous down counter, the initial content is ____________
A. 000
B. 111
C. 010
D. 101
Answer: A
Clarification: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first negative transition of the clock, the counter content becomes 101.

8. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
A. 000
B. 111
C. 101
D. 010
Answer: B
Clarification: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 111.

9. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
A. 000
B. 111
C. 101
D. 010
Answer: C
Clarification: Since, in the down counter, the counter content is decremented by 1 for every negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes 101.

10. The hexadecimal equivalent of 15,536 is ________
A. 3CB0
B. 3C66
C. 63C0
D. 6300
Answer: A
Clarification: You just divide the number by 16 at the end and store the remainder from bottom to top.

11. In order to check the CLR function of a counter ____________
A. Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state
B. Ground the CLR input and check to be sure that all of the Q outputs are LOW
C. Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
D. Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling
Answer: A
Clarification: CLR stands for clearing or resetting all states of flip-flop. In order to check the CLR function of a counter, apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state.

250+ TOP MCQs on Read Only Memory (ROM) – 3 and Answers

Digital Electronic/Circuits Aptitude Test on “Read Only Memory(ROM)-3”.

1. ROM may be programmed in _____ ways.
A. 2
B. 3
C. 4
D. 5
Answer: A
Clarification: ROM may be programmed in two different ways: (i) Mask Programming & (ii) PROM. Mask Programming is done by the manufacture. Whereas, PROM(Programmable ROM) is programmed by the user.

2. Which programming is done during the manufacturing process?
A. Mask Programming
B. PROM
C. Both PROM and mask programming
D. EPROM
Answer: A
Clarification: Mask ROM is permanently programmed during the manufacturing process. Whereas, PROM(Programmable ROM) is programmed by the user.

3. A photographic negative is called a ____________
A. Photo
B. Negative
C. Mask
D. Virtual image
Answer: C
Clarification: A photographic negative is called a mask is used to control the electrical connections on the chip.

4. Mask programming is also known as __________
A. EPROM
B. PROM
C. Custom programming
D. Both PROM and EPROM
Answer: C
Clarification: Mask programming is also known as custom programming. Mask ROM is permanently programmed during the manufacturing process. Whereas, PROM(Programmable ROM) is programmed by the user.

5. The total storage capacity of 16 * 8 ROM is __________
A. 8 bits
B. 16 bits
C. 128 bits
D. 64 bits
Answer: C
Clarification: ROM stands for Read Only Memory in which data is stored permanently and wherefrom data can only be read and rarely modified. The total storage capacity of 16 * 8 ROM is 128 bits (i.e. 16 * 8 = 128).

6. Which IC is a typical MSI/TTL based?
A. IC 74187
B. IC 74189
C. IC 74188
D. IC 74186
Answer: A
Clarification: MSI/TTL stands for Medium Scale Integration of Transistor-Transistor Logic. IC 74187 is a typical MSI/TTL based.

7. IC 74187 is of __________
A. 512 bits
B. 1024 bits
C. 256 bits
D. 68 bits
Answer: B
Clarification: IC 74187 is of 1024 bits because it is organised as 256 * 4. Thus, it has 256 rows and 4 columns.

8. How many rows and columns are present in IC 74187?
A. 128, 3
B. 128, 4
C. 256, 3
D. 256, 4
Answer: D
Clarification: IC 74187 is organised as 256 * 4, hence it has 256 rows and 4 columns.
IC 74187 is of 1024 bits because it is organized as 256 * 4.

9. Which of the following IC is of 256 bit?
A. IC 74187
B. IC 74189
C. IC 74188
D. IC 74186
Answer: C
Clarification: IC 74188 is of 256 bits. Since, it is organised as 32 * 8 = 256. Thus, it has 32 rows and 8 columns.

10. Which IC is known as bipolar ROM?
A. IC 74187
B. IC 74189
C. IC 74188
D. IC 74186
Answer: C
Clarification: IC 74188 is known as bipolar ROM since it is made up of TTL logic.

11. How many address location a bipolar ROM has?
A. 16
B. 32
C. 64
D. 8
Answer: B
Clarification: Bipolar ROM means IC 74188 and it is organized as 32 * 8. Thus, it has 32 rows and 8 columns. So, it has 32 address locations and each of which has 8 bits of storage.

12. Which of the following is known as MOS static ROM?
A. TMS 45276
B. TMS 45278
C. TMS 45279
D. TMS 45275
Answer: A
Clarification: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs.

13. TMS 45276 is of __________
A. 32 KB
B. 56 KB
C. 8 bits
D. 4 bytes
Answer: A
Clarification: TMS 45276 is known as MOS static ROM and it is made up of MOSFETs. In ROM, the data remains even when the power is switched off. TMS 45276 is of 32 KB.

14. Which of the following has the capability to store the highest bits of data?
A. TMS 45276
B. IC 74188
C. IC 74187
D. IC 74185
Answer: A
Clarification: TMS 45276 has the capability to store the highest bits of data because of 32768 * 8 = 12,62,144 organization.

15. What does CS mean in a chip?
A. Storing Capacity
B. Custom Select
C. Chip Select
D. Custom Storage
Answer: C
Clarification: CS means chip select and with the help of CS a chip is activated/deactivated. It is used for enabling or disabling the function of the chip.

16. ROMs are used to __________
A. Store bootstrap program
B. Character generation
C. Code conversion
D. All of the Mentioned
Answer: D
Clarification: ROM stands for Read Only Memory in which data is permanently stored, even when the power is turned off. It is used to store bootstrap program, character generation and code conversion.

for aptitude tests,

250+ TOP MCQs on Logic Gates and Networks – 1 and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Logic Gates and Networks – 1”.

1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	0

INPUT		OUTPUT
A	B	C
0	0	1
0	1	0
1	0	0
1	1	1

The gate is either _________
A. A NAND or an EX-OR
B. An OR or an EX-NOR
C. An AND or an EX-OR
D. A NOR or an EX-NOR
Answer: D
Clarification: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in the above table).

2. The code where all successive numbers differ from their preceding number by single bit is __________
A. Alphanumeric Code
B. BCD
C. Excess 3
D. Gray
Answer: D
Clarification: The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next. BCD Code is one in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the decimal numbers are incremented by 3 and then written in their BCD format.

3. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
A. 2 to 4 line
B. 3 to 8 line
C. 4 to 16 line
D. 5 to 32 line
Answer: C
Clarification: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

4. How many AND gates are required to realize Y = CD + EF + G?
A. 4
B. 5
C. 3
D. 2
Answer: D
Clarification: To realize Y = CD + EF + G, two AND gates are required and two OR gates are required.

5. The NOR gate output will be high if the two inputs are __________
A. 00
B. 01
C. 10
D. 11
Answer: A
Clarification: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be 00.

6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
A. 2, 2
B. 2, 3
C. 3, 3
D. 3, 2
Answer: A
Clarification: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

7. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
A. OR
B. AND
C. XOR
D. NAND
Answer: D
Clarification: An Universal Logic Gate is one which can generate any logic function and also the three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function and are thus Universal Logic Gates.

8. A full adder logic circuit will have __________
A. Two inputs and one output
B. Three inputs and three outputs
C. Two inputs and two outputs
D. Three inputs and two outputs
Answer: D
Clarification: A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
A. 3, 2
B. 4, 2
C. 1, 1
D. 2, 3
Answer: A
Clarification: There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

10. Which of the following are known as universal gates?
A. NAND & NOR
B. AND & OR
C. XOR & OR
D. EX-NOR & XOR
Answer: A
Clarification: The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates, and also they can generate the 3 basic gates AND, OR and NOT.

11. The gates required to build a half adder are __________
A. EX-OR gate and NOR gate
B. EX-OR gate and OR gate
C. EX-OR gate and AND gate
D. EX-NOR gate and AND gate
Answer: C
Clarification: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

250+ TOP MCQs on Half & Full Subtractor and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Half & Full Subtractor”.

1. Half subtractor is used to perform subtraction of ___________
A. 2 bits
B. 3 bits
C. 4 bits
D. 5 bits
Answer: A
Clarification: Half subtractor is a combinational circuit which is used to perform subtraction of two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.

2. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
A. Carry
B. Borrow
C. Input
D. Output
Answer: B
Clarification: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because carry is taken into consideration during addition process.

3. How many outputs are required for the implementation of a subtractor?
A. 1
B. 2
C. 3
D. 4
Answer: B
Clarification: There are two outputs required for the implementation of a subtractor. One for the difference and another for borrow.

4. Let the input of a subtractor is A and B then what the output will be if A = B?
A. 0
B. 1
C. A
D. B
Answer: A
Clarification: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In both of the situation subtractor gives 0 as the output.

5. Let A and B is the input of a subtractor then the output will be ___________
A. A XOR B
B. A AND B
C. A OR B
D. A EXNOR B
Answer: A
Clarification: The subtractor has two outputs BORROW and DIFFERENCE. Since the difference output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final difference output is AB’ + BA’.

6. Let A and B is the input of a subtractor then the borrow will be ___________
A. A AND B’
B. A’ AND B
C. A OR B
D. A AND B
Answer: B
Clarification: The borrow of a subtractor is received through AND gate whose one input is inverted. On that basis the borrow will be (A’ AND B..

7. What does minuend and subtrahend denotes in a subtractor?
A. Their corresponding bits of input
B. Its outputs
C. Its inputs
D. Borrow bits
Answer: C
Clarification: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the two inputs of a subtractor then A is called minuend and B as subtrahend.

8. Full subtractor is used to perform subtraction of ___________
A. 2 bits
B. 3 bits
C. 4 bits
D. 8 bits
Answer: B
Clarification: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs BORROW and DIFFERENCE.

9. The full subtractor can be implemented using ___________
A. Two XOR and an OR gates
B. Two half subtractors and an OR gate
C. Two multiplexers and an AND gate
D. Two comparators and an AND gate
Answer: B
Clarification: A full subtractor has 3 input bits and two outputs bits BORROW and DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR gate.

10. The output of a subtractor is given by (if A, B and X are the inputs).
A. A AND B XOR X
B. A XOR B XOR X
C. A OR B NOR X
D. A NOR B XOR X
Answer: B
Clarification: The difference output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR X.

11. The output of a full subtractor is same as ____________
A. Half adder
B. Full adder
C. Half subtractor
D. Decoder
Answer: B
Clarification: The sum and difference output of a full adder and a full subtractor are same. If A, B and C are the input of a full adder and a full subtractor then the output will be given by (A XOR B XOR C., respectively.