This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Overloading”.
1. What is the meaning of overloading?
a) To use single function many times
b) To use same object for different subprograms
c) To use same name for different objects
d) To use single function many time with single call
Clarification: An object is said to be overloaded when the same object name exists for multiple subprograms or types. In VHDL different type of overloading is possible such as subprogram overloading, operator overloading etc.
2. Overloading a subprogram allows subprogram to ________
a) Operate on objects of different types
b) Operate on objects of same name
c) Operate on objects of different name
d) Operate on objects of same types
Clarification: Overloading a subprogram means to use a single name which has multiple definitions. It allows subprograms to operate on objects of different types. For example, a user define function my_func is called with two different object one of bit_vector type and another of integer type, in this case my_func must be defined twice.
3. Using overloaded subprograms and operators increase readability of code.
Clarification: The result of using overloaded subprograms and operators is models that are easier to read and maintain. It frees the designer from the necessity of generating countless unique names for subprograms that do virtually the same operation.
4. What is the necessary condition to overload parameters type of a subprogram?
a) The base type of two parameters must be same
b) The parameters must have a different name
c) The parameters can’t be of integer type
d) The base type of two parameters must differ
Clarification: To overload argument types, the base type of parameters of two functions must be different. For example, base types do not differ when two subtypes are of the same type, in that case compiler will return an error.
5. By overloading + operator, it is possible to _________
a) Use binary addition
b) Use arithmetic addition
c) Use it as subtract operator
d) Use it as ternary operator
Clarification: Overloading an operator allows the operator to perform the same operations on multiple types. In this case, + operator is predefined for arithmetic operation, it can be overloaded to perform the same on binary numbers.
6. Which of the following is true about the overloading of ‘+’ and ‘-‘ operators?
a) They can be defined as binary operators only
b) They can be defined as unary operators only
c) They can be defined as ternary operators only
d) They can be defined as either binary or unary operators
Clarification: These are the two operators which can be defined as both binary as well as unary operators. Binary operators are those which take two operands and unary operators take a single operator. It is not possible to define them as ternary operators.
7. Apart from subprogram and operator overloading, which of the following can be overloaded in VHDL?
c) IF statement
d) CASE statement
Clarification: Overloading of enumeration types is also possible in case of VHDL apart from operator and subprogram overloading. This means that different types can have same name just like subprogram overloading.
8. Which of the following function definition will return an error?
SUBTYPE log4 IS BIT_VECTOR (0 TO 3) SUBTYPE log8 IS BIT_VECTOR (0 TO 7) FUNCTION abc (a : log4) RETURN INTEGER; FUNCTION abc (a : log8) RETURN INTEGER;
a) Only first call
b) Only second call
c) Both first and second call
d) No error
Clarification: Here the function abc is overloaded and both has parameters which also have same name or they are also overloaded. So, the base type of two parameters must be different. Here both have same base type which is BIT_VECTOR. Therefore, the second function will be illegal and the error is that two functions have been declared for same base type.
9. A user wants to perform a different operation on an array type and the function can be overloaded but the parameter is of same base type. How to do the same by using a single function?
a) By using conditional statement with ‘LENGTH attribute
b) By using loop statement with ‘LENGTH attribute
c) By using unconstrained array in parameters
d) It can’t be done by using single function
Clarification: Since the parameter is of same base type, it is just that it has different length. So, there is no need to overload the function. It can be defined in a single function only by using conditional statements. For example, one can do it like shown below:
IF(parameter’LENGTH =n) THEN do_this; ELSE do_this
10. In the two functions defined below, which would generate an error?
FUNCTION abc ( a, b: std_logic) RETURNS BOOLEAN; FUNCTION abc( a, b, c: std_logic) RETURNS BOOLEAN;
a) Only function 1
b) Only function 2
c) Both functions 1 and 2
d) No error
Clarification: In case of subprogram overloading, either base type or number of parameters must be different. If the number of parameters are same, then parameters can have same name. But, if both functions have same number of parameters, then the names of parameters must differ.
11. It is possible to define a new operator ++ in VHDL.
Clarification: Yes, It is the important point to note that we can overload any predefined operator in VHDL, but it is not legal to define new components in VHDL. This is the common mistake which beginners make, we can’t define a new operator.
12. What is the correct syntax to define a function which overloads any operator, say + operator for bit_vector type?
a) FUNCTION + (L : bit_vector, R : bit_vector) RETURN bit_vector IS
b) FUNCTION ‘+’ (L : bit_vector, R : bit_vector) RETURN bit_vector IS
c) FUNCTION “+” (L : bit_vector, R : bit_vector) RETURN bit_vector IS
d) FUNCTION (+) (L : bit_vector, R : bit_vector) RETURN bit_vector IS
Clarification: Function overloading and operator overloading both are same except one point which is operator which is to be overloaded must be placed in double quotation marks. Otherwise, the syntax for both type of overloading is same.