# 250+ TOP MCQs on Peak Detector, Sampling & Hold Circuit and Absolute Value Output Circuit & Answers

Linear Integrated Circuit Multiple Choice Questions on “Peak Detector, Sampling & Hold Circuit and Absolute Value Output Circuit “.

1. Which circuit can be used as a full wave rectifier?
A. Absolute vale output circuit
B. Positive clipper with two diodes
C. Negative clipper with two diodes
D. Peak clampers

Clarification: Absolute value output circuit produces an output signal that swings positively only, regardless of the polarity of the input signal; because of the nature of its output wave form, the circuit is used as full wave rectifier.

2. For the circuit shown below find the output voltage
A. Vo (+) = +10 v
B. Vo (+) = +12v
C. Vo (+) = +7v
D. None of the mentioned

Clarification: The voltage at the terminal V1 = (Vp -Vd1) /2
V1 = (12-0.7) /2 = 5.65 v (Vd1= voltage drop across diode=0.7)
Similarly, the voltage at the negative terminal V2 = (Vo -Vd3 ) /2 = (Vo – 0.7) /2
Since Vid ≅ 0v , ∴ V1 = V2
Vo = (5.65 *2 ) + 0.7 = 12v.

4. What is the alternate method to measure the values of non-sinusoidal waveform other than ac voltmeter?
A. Clipper
B. Clamper
C. Peak detector
D. Comparator

Clarification: A conventional ac voltmeter is designed to measure rms value of the pure sine wave whereas, the peak value of the non-sinusoidal wave forms can be a peak detector.

5. State the condition needed to be satisfied by peak detector for proper operation of circuit.
A. CRd ≤ T/10 and CRL ≥ 10T
B. CRd ≤ 10T and CRL ≥ T/10
C. CRd ≥ T/10 and CRL ≤ 10T
D. CRd ≥ 10T and CRL ≤ T/10

Clarification: For proper operation of the circuit, charging and discharging time constant must satisfy the following: CRd ≤ T/10 and CRL ≥ to 10T.

6. The resistor in the peak detector are used to
A. To maintain proper operation
B. Protect op-amp from damage
C. To get shaped non-sinusoidal waveform
D. None of the mentioned

Clarification: The resistor is used to protect the op-amp against the excessive discharge current, especially when the power supply is switched off.

7. How the recovery time of the op-amp is reduced?
A. Diode is connected at the output of amplifier
C. Forward biased diode resistor
D. Discharge capacitor

Clarification: The diode connected at the output of op-amp conducts during negative half cycle of input voltage. Hence, prevent the op-amp from going into negative saturation. This in turn helps to reduce the recovery time of the op-amp.

8. How to detect the negative peaks of input signals in the peak detector given below?

A. Reversing D1 diode
B. Reversing D1 and D2 diodes
C. Reversing D2 diode
D. Charging the positions of D1 and D2

Clarification: The negative peaks of the input signal Vin can be detected by reversing diodes D1 and D2.

9. In the sample and hold circuit, the period during which the voltage across capacitor is equal to input voltage
A. Sample period
B. Hold period
C. Delay period
D. Charging period

Clarification: The time periods of the sample and hold control voltage during which the voltage across capacitor is equal to the input voltage are called sample period.

10. During which period the op-amps output of sample and hold circuits is processed?
A. Delay period
B. Sample and hold period
C. Sample period
D. Hold period

Clarification: Hold period is the period during which the voltage across the capacitor is constant and the output of the op-amp is processed or observed during hold periods.

11. Which IC is mostly preferred for sample and hold circuit?
A. µ771
B. IC741
C. LF398
D. µ351