250+ TOP MCQs on Up Down Counter and Answers

Digital Electronics/Circuits Multiple Choice Questions on “Up Down Counter”.

1. UP-DOWN counter is a combination of ____________
A. Latches
B. Flip-flops
C. UP counter
D. Up counter & down counter
Answer: D
Clarification: As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well. It alternatively counts up and down.

2. UP-DOWN counter is also known as ___________
A. Dual counter
B. Multi counter
C. Multimode counter
D. Two Counter
Answer: C
Clarification: UP-DOWN counter is also known as multimode counter because it has capability of counting upward as well as downwards.

3. In an UP-counter, each flip-flop is triggered by ___________
A. The output of the next flip-flop
B. The normal output of the preceding flip-flop
C. The clock pulse of the previous flip-flop
D. The inverted output of the preceding flip-flop
Answer: B
Clarification: In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop. UP-counter counts from 0 to a maximum value.

4. In DOWN-counter, each flip-flop is triggered by ___________
A. The output of the next flip-flop
B. The normal output of the preceding flip-flop
C. The clock pulse of the previous flip-flop
D. The inverted output of the preceding flip-flop
Answer: D
Clarification: In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-flop. DOWN-counter counts from a maximum value to 0.

5. Binary counter that count incrementally and decrement is called ___________
A. Up-down counter
B. LSI counters
C. Down counter
D. Up counter
Answer: A
Clarification: Binary counter that counts incrementally and decrement is called UP-DOWN counter/multimode counter. It alternately counts up and down.

6. Once an up-/down-counter begins its count sequence, it ___________
A. Starts counting
B. Can be reversed
C. Can’t be reversed
D. Can be altered
Answer: D
Clarification: In up/down ripple counter once the counting begins, we can simply change the pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

7. In 4-bit up-down counter, how many flip-flops are required?
A. 2
B. 3
C. 4
D. 5
Answer: C
Clarification: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4 J-K flip-flops required.

8. A modulus-10 counter must have ________
A. 10 flip-flops
B. 4 Flip-flops
C. 2 flip-flops
D. Synchronous clocking
Answer: B
Clarification: 2^n-1 < = N < = 2ⁿ
For modulus-10 counter, N = 10. Therefore, 2³ < = 10 < = 2⁴. Thus, n = 4, and therefore, we require 4 FFs.

9. Which is not an example of a truncated modulus?
A. 8
B. 9
C. 11
D. 15
Answer: A
Clarification: An n-bit counter whose modulus is less than the maximum possible is called a truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a truncated counter.

10. The designation means that the ________
A. Up count is active-HIGH, the down count is active-LOW
B. Up count is active-LOW, the down count is active-HIGH
C. Up and down counts are both active-LOW
D. Up and down counts are both active-HIGH
Answer: A
Clarification: The designation means that the up count is active-HIGH, the down count is active-LOW. Active-High means that up-count would be triggered when clock is 1 else when clock is 0, down-count would be triggered, which is referred to as Active-low.

11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
A. Taking the output on the other side of the flip-flops (instead of Q)
B. Clocking of each succeeding flip-flop from the other side (instead of Q)
C. Changing the flip-flops to trailing edge triggering
D. All of the Mentioned
Answer: D
Clarification: By all of the mentioned ideas, an asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs refer to FFs being triggered during a clock transition from LOW to HIGH or HIGH to LOW.

12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________
A. 1.25 kHz
B. 2.50 kHz
C. 160 kHz
D. 320 kHz
Answer: A
Clarification: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.