This set of VHDL Multiple Choice Questions & Answers (MCQs) on User defined Data Types”.
1. How the keyword “TYPE” is used?
a) TYPE datatype_name IS type_from_predefined_datatypes;
b) TYPE datatype_name IS datatype_range;
c) TYPE datatype_range IS datatype_name;
d) USE TYPE datatype_range IS datatype_name;
Answer: b
Clarification: The keyword TYPE is used to define new data type if any user wants to define for its own. The syntax for keyword is- TYPE datatype_name IS datatype_range. So, the new data type can have the values defined in range section of the declaration.
2. Which of the following is a wrong declaration for a new data type?
a) TYPE my_logic IS RANGE 0 to 100;
b) TYPE my_logic IS (‘0’, ‘1’, ‘2’);
c) TYPE my_logic IS ARRAY (0 TO 3) OF BIT;
d) TYPE my_logic IS <0 TO 20 >
Answer: d
Clarification: TYPE can be used in three forms as shown above. For defining range, there are two methods as illustrated in option TYPE my_logic IS RANGE 0 to 100; and option TYPE my_logic IS (‘0’, ‘1’, ‘2’);. If we want to define a user defined array then the sytanx like option TYPE my_logic IS ARRAY (0 TO 3) OF BIT; follows. But, we can’t define range by using <> sign.
3. One can’t define an array without any constraints in VHDL.
a) True
b) False
Answer: b
Clarification: We can define an array without any constraints in VHDL. When there are no constraints in array then it can have any number of elements. For example, TYPE my_type IS ARRAY (RANGE <>) OF BIT; this declaration defines an array of BIT data type without any constraint on the number of elements in the array.
4. A SUBTYPE can be defined as _________
a) A TYPE under a TYPE (nested)
b) A type of INTEGER datatype
c) A TYPE with some constraint
d) A TYPE without any constraint
Answer: c
Clarification: A SUBTYPE is a TYPE with some constraints. TYPE can be predefined data type and it can also be any user defined data type. But if SUBTYPE is derived from user defined datatype, then we first have to declare the type along with its range and then subtype can be defined.
5. Which of the following is the correct syntax for declaring a SUBTYPE?
a) TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
b) SUBTYPE subtype_name IS subtype_range TYPE type_name
c) SUBTYPE subtype_name TYPE type_name IS subtype_range
d) SUBTYPE subtype_name IS TYPE subtype_range
Answer: d
Clarification: The correct way to define a SUBTYPE is the syntax shown in option d. For example, if we want to define a SUBTYPE of STD_LOGIC with 3 values only like X, 0 and 1. We can define it as SUBTYPE my _ subtype IS STD_LOGIC RANGE ‘X’ TO ‘1’.
6. Which of the following can’t be the value of x? Refer to the VHDL code given below.
TYPE color IS (red, green, blue, black, white, gray); SUBTYPE primary IS color RANGE red to blue; VARIABLE x: primary;
a) White
b) Red
c) Green
d) Blue
Answer: a
Clarification: PRIMARY is a subtype of COLOR as declared in the code. The range of PRIMARY is declared “red” to “blue”. It means that an object of Primary type can have values red, green or blue. So White can’t be assigned to x.
7. Look at the following declarations:
TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;
How many total bits can be stored in these arrays?
a) 16
b) 9
c) 64
d) 27
Answer: c
Clarification: First of all, array1 is array of BIT_VECTOR type that means it contains 4 BIT_VECTOR. One BIT_VECTOR is here declared to be consisting of 4 bits. Therefore, Array 1 can have 16 bits. Now, array2 is an array of 4 array1. Therefore, total bits are 4 × 16 = 64.
8. Refer to the four declarations below, which of the following is not a 2 dimensional array?
TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC; TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 ); TYPE array3 IS ARRAY (2 DOWNTO 0 ) OF array2; TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;
a) array4
b) array3
c) array2
d) array1
Answer: b
Clarification: Here, array1 is a 2-D array with 4 rows and 2 columns (3 DOWNTO 0 and 1 DOWNTO 0) of STD_LOGIC type. Though, array2 declaration looks like 1D array, but it is 2D array, since it is of type STD_LOGIC_VECTOR, which is already a 1D array, so array2 is a 2D array. Similarly array4 is 4 × 4 matrix. But, array3 is a 3D array. Because it is 1D array of 2D array named as array2.
9. User can define its own integer data type.
a) True
b) False
Answer: a
Clarification: In VHDL, user can define either its own integer type or enumerated type. User defined integer type must always be a subset of predefined datatype. User can define the integer with some desired range. For example, we can define any integer named as my_integer with range 0 to 32 as given: TYPE my_integer IS RANGE 0 TO 32; in this way, one can define a subset of integer.
10. Which of the following is a SUBTYPE of INTEGER?
a) NATURAL
b) REAL
c) CHARACTER
d) STD_LOGIC
Answer: a
Clarification: We can say that NATURAL is a subtype of INTEGER. The range of NATURAL datatype is 0 to 231-1, whereas the range of INTEGER is – (231-1) to (231-1). Therefore, it can be written as SUBTYPE NATURAL IS INTEGER RANGE 0 TO 2147483647.