This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Top Level System Design”.
1. The top-level system design is modelled for functionality and performance.
a) True
b) False
Answer: a
Clarification: In the top-level system design each major component in the design is formed at the gate level and the design is simulated again for the timing, functionality and performance.
2. Which modelling is used in the top-level system design?
a) Low-level behavioural modelling
b) High-level behavioural modelling
c) Structural modelling
d) Data flow modelling
Answer: b
Clarification: High-level behavioural modelling is used in the top-level system design. It is the highest level of abstraction in the VHDL. This level simulates the behavioural level of the circuits and the development rate at this level is highest.
3. What are the two constructs used in most of the behavioural modelling?
a) Assign
b) Begin and end
c) Initial and always
d) Always and end
Answer: c
Clarification: The two constructs used in most of the behavioural modelling are Initial and always. All the other behavioural statements appear only inside these two structured procedure constructs.
4. How many levels of abstraction are there in the top-level system design?
a) One
b) Two
c) Three
d) Four
Answer: c
Clarification: There are three levels of abstraction: algorithm, register transfer level (RTL), and gate level. Algorithms cannot be synthesized, RTL is the input to the synthesis, gate level is the output from the synthesis.
5. Timing performance of design is checked by which of the following simulation mode?
a) Gate-level
b) Behavioural
c) Transistor-level
d) Switch-level
Answer: a
Clarification: Gate-level simulation is used to check the timing performance of a design. It quickly does the implementation of the design and helps in verifying the dynamic behaviour of the circuit which is usually not verified correctly by the static methods.
6. The statements in the initial construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: b
Clarification: The statements in the initial construct constitute the initial block. Initial block is executed only once during the simulation process, at time 0. If there are more than one initial blocks, then all the initial blocks are executed simultaneously.
7. The statements in the always construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: d
Clarification: The statements in the always construct constitute the always block. The always block starts executing at time 0 and keeps on executing during the complete simulation process. It is like an infinite loop.
8. Register data types and memory data types are updated by procedural assignments.
a) True
b) False
Answer: a
Clarification: Procedural assignments update reg, integer, real, time, real-time, and memory data types. The values in procedural assignments change the procedural flow constructs. The variables hold their values until they’re updated by another procedural assignment.
9. How many types of procedural assignments are there?
a) One
b) Two
c) Three
d) Four
Answer: b
Clarification: There are two types of procedural assignments which are blocking and non-blocking assignments. Blocking assignment doesn’t block the execution of the next statement. The non-blocking assignment allows for assignment scheduling.
10. In which order do the blocking assignment statements are executed in a sequential block?
a) Random order
b) Specified order
c) Ascending order
d) Descending order
Answer: b
Clarification: Blocking assignment statements are executed in a SPECIFIED order in a sequential block. The next statement executes only after the present blocking assignments are completed. A blocking assignment doesn’t block the execution of an upcoming statement in a parallel block.