Microprocessor Multiple Choice Questions on “Features of Pentium 4, Netburst Microarchitecture For Pentium4 – 1”.
1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
Answer: d
Clarification: Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from 1.4GHz to 1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
Answer: c
Clarification: Pentium 4 architecture may be viewed having four basic modules.
1. Front end module
2. Out of order execution engine
3. Execution module
4. Memory subsystem module.
3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
Answer: d
Clarification: The front module of Pentium 4 contains
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor.
4. The unit that decodes the instructions concurrently and translate them into micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
Answer: b
Clarification: The role of instruction decoder is to decode the instructions concurrently and translate them into micro-operations known as micro-ops.
5. In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: c
Clarification: In case of complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to microcode ROM.
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: a
Clarification: The trace cache is a special instruction cache because it does not store the instructions, but the decoded stream of instructions.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
Answer: d
Clarification: Trace cache can store upto 12K micro-ops. The cache assembles the decoded micro-ops into ordered sequence of micro-ops called traces.
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: b
Clarification: The front end branch predictor predicts the locations from where the next instruction bytes are fetched.
9. If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
Clarification: When some complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to microcode ROM.
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder