Category: Digital Circuits Objective Questions

Digital Electronics/Circuits Multiple Choice Questions on “K-Map Simplification”.

1. Which statement below best describes a Karnaugh map?
A. It is simply a rearranged truth table
B. The Karnaugh map eliminates the need for using NAND and NOR gates
C. Variable complements can be eliminated by using Karnaugh maps
D. A Karnaugh map can be used to replace Boolean rules
Answer: A
Clarification: K-map is simply a rearranged truth table. It is a pictorial representation of truth table having a specific number of cells or squares, where each cell represents a Maxterm or a Minterm.

2. Which of the examples below expresses the commutative law of multiplication?
A. A + B = B + A
B. A • B = B + A
C. A • (B • C. = (A • B. • C
D. A • B = B • A
Answer: D
Clarification: The commutative law of multiplication is (A * B. = (B * A..
The commutative law of addition is (A + B. = (B + A..

3. The Boolean expression Y = (AB.’ is logically equivalent to what single gate?
A. NAND
B. NOR
C. AND
D. OR
Answer: A
Clarification: If A and B are the input for AND gate the output is obtained as AB and after inversion we get (AB.’, which is the expression of NAND gate. NAND gate produces high output when any of the input is 0 and produces low output when all inputs are 1.

4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is referred to as __________________
A. A Karnaugh map
B. DeMorgan’s second theorem
C. The commutative law of addition
D. The associative law of multiplication
Answer: B
Clarification: DeMorgan’s Law: ~(P+Q) (~P).(~Q) Also,
~(P.Q) (~P)+(~Q).

5. The systematic reduction of logic circuits is accomplished by _______________
A. Symbolic reduction
B. TTL logic
C. Using Boolean algebra
D. Using a truth table
Answer: C
Clarification: The systematic reduction of logic circuits is accomplished by using boolean algebra.

6. Each “1” entry in a K-map square represents _______________
A. A HIGH for each input truth table condition that produces a HIGH output
B. A HIGH output on the truth table for all LOW input combinations
C. A LOW output for all possible HIGH input conditions
D. A DON’T CARE condition for all possible input truth table combinations
Answer: A
Clarification: Each “1” entry in a K-map square represents a HIGH for each input truth table condition that produces a HIGH output. Thus, it represents a minterm.

7. Each “0” entry in a K-map square represents _______________
A. A HIGH for each input truth table condition that produces a HIGH output
B. A HIGH output on the truth table for all LOW input combinations
C. A LOW output for all possible HIGH input conditions
D. A DON’T CARE condition for all possible input truth table combinations
Answer: A
Clarification: Each “0” entry in a K-map square represents a LOW output for all possible HIGH input conditions. Thus, it represents Maxterm.

8. Which of the following statements accurately represents the two BEST methods of logic circuit simplification?
A. Actual circuit trial and error evaluation and waveform analysis
B. Karnaugh mapping and circuit waveform analysis
C. Boolean algebra and Karnaugh mapping
D. Boolean algebra and actual circuit trial and error evaluation
Answer: C
Clarification: The two BEST methods of logic circuit simplification are Boolean algebra and Karnaugh mapping. Boolean Algebra uses the Laws of Boolean Algebra for minimization of Boolean expressions while Karnaugh Map is a pictorial representation and reduction of the Boolean expression.

9. Looping on a K-map always results in the elimination of __________
A. Variables within the loop that appear only in their complemented form
B. Variables that remain unchanged within the loop
C. Variables within the loop that appear in both complemented and uncomplemented form
D. Variables within the loop that appear only in their uncomplemented form
Answer: C
Clarification: Looping on a K-map always results in the elimination of variables within the loop that appear in both complemented and uncomplemented form.

10. Which of the following expressions is in the sum-of-products form?
A. (A + B.(C + D.
B. (A * B.(C * D.
C. A* B *(CD.
D. A * B + C * D
Answer: D
Clarification: Sum of product means that it is the sum of all product terms. Thus, the number is multiplied first and then it is added: A * B + C * D.

11. Which of the following is an important feature of the sum-of-products form of expressions?
A. All logic circuits are reduced to nothing more than simple AND and OR operations
B. The delay times are greatly reduced over other forms
C. No signal must pass through more than two gates, not including inverters
D. The maximum number of gates that any signal must pass through is reduced by a factor of two
Answer: A
Clarification: An important feature of the sum-of-products form of expressions in the given option is that all logic circuits are reduced to nothing more than simple AND and OR operations. Sum Of Product means it is the sum of product terms containing variables in complemented as well as uncomplemented forms.

12. Which of the following expressions is in the product-of-sums form?
A. (A + B.(C + D.
B. (AB.(CD.
C. AB(CD.
D. AB + CD
Answer: A
Clarification: (A + B.(C + D. represents the product-of-sums form.

Digital Electronics/Circuits Multiple Choice Questions on “Up Down Counter”.

1. UP-DOWN counter is a combination of ____________
A. Latches
B. Flip-flops
C. UP counter
D. Up counter & down counter
Answer: D
Clarification: As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well. It alternatively counts up and down.

2. UP-DOWN counter is also known as ___________
A. Dual counter
B. Multi counter
C. Multimode counter
D. Two Counter
Answer: C
Clarification: UP-DOWN counter is also known as multimode counter because it has capability of counting upward as well as downwards.

3. In an UP-counter, each flip-flop is triggered by ___________
A. The output of the next flip-flop
B. The normal output of the preceding flip-flop
C. The clock pulse of the previous flip-flop
D. The inverted output of the preceding flip-flop
Answer: B
Clarification: In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop. UP-counter counts from 0 to a maximum value.

4. In DOWN-counter, each flip-flop is triggered by ___________
A. The output of the next flip-flop
B. The normal output of the preceding flip-flop
C. The clock pulse of the previous flip-flop
D. The inverted output of the preceding flip-flop
Answer: D
Clarification: In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-flop. DOWN-counter counts from a maximum value to 0.

5. Binary counter that count incrementally and decrement is called ___________
A. Up-down counter
B. LSI counters
C. Down counter
D. Up counter
Answer: A
Clarification: Binary counter that counts incrementally and decrement is called UP-DOWN counter/multimode counter. It alternately counts up and down.

6. Once an up-/down-counter begins its count sequence, it ___________
A. Starts counting
B. Can be reversed
C. Can’t be reversed
D. Can be altered
Answer: D
Clarification: In up/down ripple counter once the counting begins, we can simply change the pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

7. In 4-bit up-down counter, how many flip-flops are required?
A. 2
B. 3
C. 4
D. 5
Answer: C
Clarification: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are 4 J-K flip-flops required.

8. A modulus-10 counter must have ________
A. 10 flip-flops
B. 4 Flip-flops
C. 2 flip-flops
D. Synchronous clocking
Answer: B
Clarification: 2^n-1 < = N < = 2ⁿ
For modulus-10 counter, N = 10. Therefore, 2³ < = 10 < = 2⁴. Thus, n = 4, and therefore, we require 4 FFs.

9. Which is not an example of a truncated modulus?
A. 8
B. 9
C. 11
D. 15
Answer: A
Clarification: An n-bit counter whose modulus is less than the maximum possible is called a truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas, modulus-8 is not a truncated counter.

10. The designation means that the ________
A. Up count is active-HIGH, the down count is active-LOW
B. Up count is active-LOW, the down count is active-HIGH
C. Up and down counts are both active-LOW
D. Up and down counts are both active-HIGH
Answer: A
Clarification: The designation means that the up count is active-HIGH, the down count is active-LOW. Active-High means that up-count would be triggered when clock is 1 else when clock is 0, down-count would be triggered, which is referred to as Active-low.

11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
A. Taking the output on the other side of the flip-flops (instead of Q)
B. Clocking of each succeeding flip-flop from the other side (instead of Q)
C. Changing the flip-flops to trailing edge triggering
D. All of the Mentioned
Answer: D
Clarification: By all of the mentioned ideas, an asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs refer to FFs being triggered during a clock transition from LOW to HIGH or HIGH to LOW.

12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________
A. 1.25 kHz
B. 2.50 kHz
C. 160 kHz
D. 320 kHz
Answer: A
Clarification: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.

Digital Electronics/Circuits Multiple Choice Questions on “Erasable Programmable Read Only Memory”.

1. EPROM uses an array of _______________
A. p-channel enhancement type MOSFET
B. n-channel enhancement type MOSFET
C. p-channel depletion type MOSFET
D. n-channel depletion type MOSFET
Answer: B
Clarification: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-programmed. EPROM uses an array of n-channel enhancement type MOSFET with an insulated gate structure.

2. The EPROM was invented by ______________
A. Wen Tsing Chow
B. Dov Frohman
C. Luis O Brian
D. J P Longwell
Answer: B
Clarification: The EPROM was invented by Dov Frohman of Intel in 1971. EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-programmed.

3. Address decoding for dynamic memory chip control may also be used for ______________
A. Chip selection and address location
B. Read and write control
C. Controlling refresh circuits
D. Memory mapping
Answer: A
Clarification: Address decoding for dynamic memory chip control may also be used for chip selection and address location. Chip Selection enables or disables the functioning of the chip.

4. Which of the following describes the action of storing a bit of data in a mask ROM?
A. A 0 is stored by connecting the gate of a MOS cell to the address line
B. A 0 is stored in a bipolar cell by shorting the base connection to the address line
C. A 1 is stored by connecting the gate of a MOS cell to the address line
D. A 1 is stored in a bipolar cell by opening the base connection to the address line
Answer: C
Clarification: The action of storing a bit of data in a mask ROM is that when a 1 is stored by connecting the gate of a MOS cell to the address line. Mask ROMs are programmed by the manufacturer and are custom made as per the user.

5. The check sum method of testing a ROM ______________
A. Allows data errors to be pinpointed to a specific memory location
B. Provides a means for locating and correcting data errors in specific memory locations
C. Indicates if the data in more than one memory location is incorrect
D. Simply indicates that the contents of the ROM are incorrect
Answer: D
Clarification: If checking of a sum method goes wrong, it simply indicates that the contents of the ROM are incorrect.

6. The initial values in all the cells of an EPROM is ______________
A. 0
B. 1
C. Both 0 and 1
D. Alternate 0s and 1s
Answer: B
Clarification: The initial values in all the cells of an EPROM is 1.

7. To store 0 in such a cell, the floating point must be ______________
A. Reprogrammed
B. Restarted
C. Charged
D. Power off
Answer: C
Clarification: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-programmed. To store 0 in the cell of an EPROM, the floating point must be charged.

8. The major disadvantage of RAM is?
A. Its access speed is too slow
B. Its matrix size is too big
C. It is volatile
D. High power consumption
Answer: C
Clarification: RAM is volatile memory. Thus, RAM stores the data as long as it is powered on and once the power goes out, it loses its data.

9. Which one of the following is used for the fabrication of MOS EPROM?
A. TMS 2513
B. TMS 2515
C. TMS 2516
D. TMS 2518
Answer: C
Clarification: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-programmed. TMS 2516 is a MOS EPROM device.

10. How many addresses a MOS EPROM have?
A. 1024
B. 512
C. 2516
D. 256
Answer: C
Clarification: EPROMs are Erasable Programmable ROMs which can be erased using UV radiation and re-programmed. MOS EPROM (i.e. TMS 2516) has 2048 (2¹¹ = 2048) addresses.

11. To read from the memory, the select input and the power down/program input must be ______________
A. HIGH
B. LOW
C. Sometimes HIGH and sometimes LOW
D. Alternate HIGH and LOW
Answer: B
Clarification: To read from the memory, the select input and the power down/program input must be LOW.

12. ROMs retain data when ______________
A. Power is on
B. Power is off
C. System is down
D. All of the Mentioned
Answer: D
Clarification: ROM retains the data when power is off/on/down because it has to read the data from memory only and it is done in every condition. It is non-volatile memory.

13. Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many bytes could be stored in this device?
A. 8,000
B. 65,536
C. 8,192
D. 64,000
Answer: C
Clarification: 8K = 8 * 1024 = 8192.

14. When a RAM module passes the checker board test it is ______________
A. Able to read and write only 0s
B. Faulty
C. Probably good
D. Able to read and write only 1s
Answer: C
Clarification: When a RAM module passes the checker board test it is probably good. It is a volatile memory. Thus, RAM stores the data as long as it is powered on and once the power goes out, it loses its data.

15. What is the difference between static RAM and dynamic RAM?
A. Static RAM must be refreshed, dynamic RAM does not
B. There is no difference
C. Dynamic RAM must be refreshed, static RAM does not
D. SRAM is slower than DRAM
Answer: C
Clarification: Dynamic RAM must be refreshed because it made up of capacitor, and capacitor required refresh. Static RAM made up of flip flop and it doesn’t required a refresh.

Digital Electronic/Circuits Questions and Answers for experienced on “Digital Integrated Circuits-2”.

1. SSI refers to ___________
A. Small Scale Integration
B. Short Scale Integration
C. Small Set Integration
D. Short Set Integration
Answer: A
Clarification: SSI refers to Small Scale Integration.

2. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
A. Fewer than 10
B. Greater than 10
C. Equal to 10
D. Greater than 50
Answer: A
Clarification: Small Scale Integration(SSI) refers to ICs with fewer than 10 gates on the same chip.

3. MSI means ___________
A. Merged Scale Integration
B. Main Scale Integration
C. Medium Scale Integration
D. Main Set Integration
Answer: C
Clarification: MSI means Medium Scale Integration.

4. MSI includes _______ gates per chip.
A. 12 to 100
B. 13 to 50
C. greater than 10
D. greater than 100
Answer: A
Clarification: Medium Scale Integration includes 12 to 100 gates per chip.

5. LSI means ________ and refers to ________ gates per chip.
A. Long Scale Integration, more than 10 upto 10000
B. Large Scale Integration, more than 100 upto 5000
C. Large Short Integration, less than 10 and greater than 5000
D. Long Short Integration, more than 10 upto 10000
Answer: B
Clarification: The full form of LSI is Large Scale Integration and refers to more than 100 upto 5000 gates per chip.

6. Integrated circuits are classified as ___________
A. Large, Small and Medium
B. Very Large, Small and Linear
C. Linear and Digital
D. Non-Linear and Digital
Answer: C
Clarification: Integrated circuits are classified as Linear and Digital. Linear operates with continuous and digital refers to discrete signals.

7. According to the IC fabrication process logic families can be divided into two broad categories as ___________
A. RTL and TTL
B. HTL and MOS
C. ECL and DTL
D. Bipolar and MOS
Answer: D
Clarification: According to the IC fabrication process logic families can be divided into two broad categories as: Bipolar and Metal-oxide semiconductor. The mentioned all others are part of bipolar. Bipolar IC fabrication refers to TTL logic where MOS refers to CMOS logic.

8. The full form of DIP is ___________
A. Dual-in-Long Package
B. Dual-in-Line Package
C. Double Integrated Package
D. Double-in-Line Package
Answer: B
Clarification: The full form of DIP is Dual-in-Line Package.

9. LCC refers to ___________
A. Longest Chip Carrier
B. Leadless Chip Carrier
C. Leaded Chip Carrier
D. Large Chip Carrier
Answer: B
Clarification: LCC refers to Leadless Chip Carrier.

10. PGA refers to ____________
A. Plastic Grid Array
B. Pin Grid Array
C. Pin Greater Array
D. Plastic Greater Array
Answer: B
Clarification: PGA refers to Pin Grid Array.

for Experienced,

Digital Electronics/Circuits Multiple Choice Questions on “Controlled Inverter”.

1. Controlled inverter is also known as _____________
A. Controlled buffer
B. NOT gate
C. Both controlled buffer and NOT gate
D. Controlled gate
Answer: C
Clarification: Controlled inverter is also known as controlled buffer and NOT gate as well. It is used between output and a bus so that one can control whether the output is fed to the bus or not.

2. Why XOR gate is called an inverter?
A. Because of the same input
B. Because of the same output
C. It behaves like a NOT gate
D. It behaves like a AND gate
Answer: C
Clarification: The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is true, the output is the inversion of the other. When one input is false, the output is the non-inversion of the other.

3. Controlled buffers can be useful __________
A. To control the circuit’s output into the bus
B. In comparison of component’s output with its input
C. In increasing the output from its low input
D. All of the Mentioned
Answer: A
Clarification: Controlled buffers can be useful when you have a wire (often called a bus) whose value should match the output of one of several components. By placing a controlled buffer between each component output and the bus, you can control whether that component’s output is fed onto the bus or not.

4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is __________
A. Ex-NOR gate
B. OR gate
C. Ex-OR gate
D. NAND gate
Answer: A
Clarification: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW. Thus, EX-NOR produces output for even number of 1’s or all 0s, while EXOR produces output for odd number of 1’s.

5. What is the first thing you will need if you are going to use a macro-function?
A. A complicated design project
B. An experienced design engineer
C. Good documentation
D. Experience in HDL
Answer: D
Clarification: HDL stands for Hardware Description Language. In order to use a macro function, one needs to have experience in HDL for representing the structure and behaviour of digital circuits.

6. What is the major difference between half-adders and full-adders?
A. Full-adders are made up of two half-adders
B. Full adders can handle double-digit numbers
C. Full adders have a carry input capability
D. Half adders can handle only single-digit numbers
Answer: C
Clarification: Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.

7. The binary subtraction of 0 – 0 = ?
A. Difference = 0, borrow = 0
B. Difference = 1, borrow = 0
C. Difference = 1, borrow = 1
D. Difference = 0, borrow = 1
Answer: A
Clarification: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.

8. How many basic binary subtraction operations are possible?
A. 1
B. 4
C. 3
D. 2
Answer: B
Clarification: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0 – 0 = 0
0 – 1 = 1 ( Borrow 1)
1 – 0 = 1
1 – 1 = 0

9. When performing subtraction by addition in the 2’s-complement system is?
A. The minuend and the subtrahend are both changed to the 2’s-complement
B. The minuend is changed to 2’s-complement and the subtrahend is left in its original form
C. The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
D. The minuend and subtrahend are both left in their original form
Answer: C
Clarification: When performing subtraction by addition in the 2’s-complement system, the minuend is left in its original form and the subtrahend is changed to its 2’s-complement. It is then added to the minuend. If the result has carry, then it’s dropped and that’s the final answer. Else, if the result has no carry, then the result is again converted to it’s 2’s complement form and that’s the final answer with a ‘negative’ sign.

10. What are the two types of basic adder circuits?
A. Sum and carry
B. Half-adder and full-adder
C. Asynchronous and synchronous
D. One and two’s-complement
Answer: B
Clarification: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2 inputs while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.

11. Which of the following is correct for full adders?
A. Full adders have the capability of directly adding decimal numbers
B. Full adders are used to make half adders
C. Full adders are limited to two inputs since there are only two binary digits
D. In a parallel full adder, the first stage may be a half adder
Answer: D
Clarification: By using maximum of two half adders we can make a full adder for the first stage of a Parallel Full adder.

12. The selector inputs to an arithmetic/logic unit (ALU) determine the __________
A. Selection of the IC
B. Arithmetic or logic function
C. Data word selection
D. Clock frequency to be used
Answer: B
Clarification: An ALU performs basic arithmetic and logic operations and stores it in the accumulator. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values such as NOT, AND and OR and any logical operations.