This set of VHDL Multiple Choice Questions & Answers (MCQs) on “Common Terms used in VHDL”.
1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
Answer: b
Clarification: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.
2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Answer: c
Clarification: Package is a collection of all the commonly used data types and subroutines so that programmers can easily use them in their design without defining the same functions again and again.
3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
Answer: a
Clarification: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.
4. An entity can have more than one architecture.
a) True
b) False
Answer: a
Clarification: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.
5. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Answer: d
Clarification: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.
6. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
Answer: a
Clarification: Bus is a special kind of signal. It may have its drivers turned off.
7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
Answer: b
Clarification: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.
8. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
Answer: d
Clarification: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.
9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
Answer: c
Clarification: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.
10. A process is the basic unit of execution in VHDL.
a) True
b) False