250+ TOP MCQs on A Generalized FET Amplifier and Answers

Electronic Devices and Circuits Multiple Choice Questions on “A Generalized FET Amplifier”.

1. Ideal maximum voltage for common drain amplifier is _________
A. 0
B. 1
C. 0.5
D. 2
Answer: b
Clarification: Similar to the transistor emitter follower, the source follower configuration itself provides a high level of buffering and a high input impedance. The actual input resistance of the FET itself is very high as it is a field effect device. This means that the source follower circuit is able to provide excellent performance as a buffer. The voltage gain is unity, although current gain is high. The input and output signals are in phase.

2. If a certain drain JFET has a transconductance of 4ms. And has external drain resistance of 1.5 ohm than ideal voltage gain will be _________
A. 4
B. 5
C. 6
D. 8
Answer: C
Clarification: The transconductance, gm is defined as
gm = ΔID / ΔVGS
so gm = Voltage gain / RD
Therefore, voltage gain = gm * RD
=4 * 1.5
=6.

3. Input resistance of common gate of the amplifier is __________
A. zero
B. infinity
C. extremely low
D. extremely high
Answer: C
Clarification: For a Common gate amplifier, Current gain is about unity, input resistance is low, output resistance is high a CG stage is a current “buffer”. It takes a current at the input that may have a relatively small Norton equivalent resistance and replicates it at the output port, which is a good current source due to the high output resistance.

4. A FET circuit has a transconductance of 2500 µ seconds and drain resistance equals to 10Kohms than voltage gain will be __________
A. 20
B. 25
C. 30
D. 35

Answer: B
Clarification: The transconductance, gm is defined as
gm = ΔID / ΔVGS
so gm = Voltage gain / RD
Therefore, voltage gain = gm * RD
=2500*10-6 * 10 * 103
= 25.

5. Voltage gain of common drain amplifier is always slightly less than _____
A. 0.5
B. 1
C. 1.5
D. 2
Answer: B
Clarification: In common drain amplifier
Writing KCL at the source node ;
Gm(vin – vout) – gmbs vout – gds vout = 0
vout vin = Gm / Gm + Gmbs + gds
Therefore gain is less than one.

6. A common gate amplifier has _______
A. low input impedance
B. high input impedance
C. infinite input impedance
D. no impedance
Answer: A
Clarification: Common gate amplifier just like common base amplifier had a very large voltage gain but input impedance is very low. Also, it gives unity current gain. Hence, the power of the amplified signal will be less.

7. D-MOSFET in case of common source amplifier can operate with gate to source voltage zero at ______
A. Peak positive point
B. Peak negative point
C. Q point
D. Origin
Answer: C
Clarification: Q-point” needs to be found for the correct biasing of the JFET amplifier circuit with single amplifier configurations of Common-source, Common-drain or Source-follower and the Common-gate available for most FET devices.

8. A common source amplifier has _______
A. no source resistance
B. no drain resistance
C. no gate resistance
D. low input impedance
Answer: a
Clarification: In a common source amplifier the source resistance is connected to the ground(i.e. is groundeD. because of which its source resistance is kept zero.

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9. The drain of FET is analogous to BJT
A. collector
B. emitter
C. base
D. drain
Answer: A
Clarification: A common collector amplifier (also known as an emitter follower) is one of three basic single-stage bipolar junction transistor (BJT) amplifier, typically used as a voltage buffer.
In this circuit the base terminal of the transistor serves as the input, the emitter is the output, and the collector is common to both. The analogous field-effect transistor circuit is the common drain amplifier and the analogous tube circuit is the cathode follower.

10. Input signal of common drain amplifier is applied to the gate through ________
A. input resistor
B. coupling capacitor
C. output capacitor
D. transformer
Answer: B
Clarification: A common-drain amplifier is also called a source-follower. Self-biasing is used in this particular circuit. The input signal is applied to the gate through a coupling capacitor, and the output signal is coupled to the load resistor through the other capacitor.

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