Microprocessor Multiple Choice Questions on “Architecture of 8051”.
1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: d
Clarification: In some instructions, the Accumulator and B register are used to store the operands.
2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Answer: b
Clarification: B register is used to store one of the operands for multiply and divide instructions. In other instructions, it may just be used as a scratch pad.
3. The registers that contain the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
Answer: c
Clarification: The set of flags of program status word contains the status information and is considered as one of the special function registers.
4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
Answer: c
Clarification: The 8051 stack is not a top-down data structure, like other Intel processors.
5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
Answer: d
Clarification: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each of the four on-chip I/O ports. It contains two 16-bit timer registers.
6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: b
Clarification: The transmit buffer of serial data buffer is a parallel-in serial-out register.
7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Answer: a
Clarification: The serial data register has two buffers. The transmit buffer is a parallel-in serial-out register and receive buffer is a parallel-in serial-out register.
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
Answer: b
Clarification: The registers, TMOD and TCON contain control and status information about timers/counters.
9. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON
Answer: d
Clarification: The registers, PCON and SCON contain control and status information about serial port.
10. The device that generates the basic timing clock signal for the operation of the circuit using crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
Answer: c
Clarification: The oscillator circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator.
11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2
Answer: d
Clarification: The arithmetic operations are performed over the operands held by the temporary registers, TMP1 and TMP2. Users cannot access these temporary registers.