VLSI Multiple Choice Questions on “FET Logic Inverter”.
1. Inverter uses D-MESFET as
A. load
B. switching device
C. controller
D. amplifier
Answer: A
Clarification: Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as switching device and D-MESFET is used as load.
2. The allowable output voltage is limited by
A. load resistance
B. load capacitance
C. barrier height
D. material used for barrier
Answer: C
Clarification: The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by the barrier height of the Schottky gate diode.
3. For depletion mode transistor, gate is connected to
A. Vdd
B. source
C. ground
D. drain
Answer: B
Clarification: For the depletion mode transistor, the gate is connected to the source and it is always on and only the characteristic curve Vgs=0 is suitable.
4. In DCFL inverter, enhancement mode device is called as
A. pull down transistor
B. pull up transistor
C. buffer
D. combiner
Answer: A
Clarification: In direct-coupled FET logic inverter, depletion mode device is called the pull-up and enhancement mode device is called as pull-down transistor.
5. Maximum voltage across enhancement mode device corresponds to minimum voltage across depletion mode device.
A. true
B. false
Answer: A
Clarification: In direct-coupled FET logic inverter, maximum voltage across enhancement mode device corresponds to minimum voltage across the depletion mode transistor.
6. When current begins to flow, output voltage
A. increases
B. decreases
C. remains constant
D. does not get affected
Answer: B
Clarification: When Vin exceeds threshold voltage, current begins to flow. Then the output voltage Vout decreases and the transistor becomes resistive.
7. Inverter threshold voltage is the point where
A. Vin = Vt
B. Vout = Vt
C. Vin = Vout
D. Vout lesser than Vin
Answer: C
Clarification: The point at which Vout = Vin, is denoted as Vinv. The transfer characteristic and Vinv can be shifted by variation of the ratio of pull-up to pull-down resistances.
8. For equal margin, Vinv is set as ______ of logic voltage swing.
A. equal
B. half of
C. one third
D. twice
Answer: B
Clarification: Since the logic high level is limited by barrier potential then for equal margins Vinv is set to half of the logic voltage swing.
9. For E-MESFET, Vinv is set in midway between
A. Vdd and Vss
B. Vt and Vin
C. Vt and Vout
D. barrier potential and ground
Answer: D
Clarification: In pull-down device that is E-MESFET, the inverter threshold voltage Vinv is set midway between barrier potential and ground.
10. To improve packing density, gate length should be smaller.
A. true
B. false
Answer: B
Clarification: To improve packing density, gate length should be larger for the pull-up device. This will reduce drain to source saturation current.
11. The ratio of Zp.u./Zp.d. for E-MESFET is
A. 1/10
B. 10/1
C. 4/1
D. 1/4
Answer: B
Clarification: For E-MESFET, the Zp.u./Zp.d. ratio is 10/1. For MESFET with Lp.u.=Lp.d., Wp.u./Wp.d. is equal to 1/10.
12. In direct coupled logic, the input transistor base is connected to
A. base output
B. emitter output
C. collector output
D. ground
Answer: C
Clarification: In direct coupled logic, the input transistor base is directly connected to the collector output without any base resistors.
13. Direct-coupled logic is easy to design.
A. true
B. false
Answer: A
Clarification: Direct-coupled logic devices have fewer components, are economical and simpler to design and fabricate.
14. For cascade inverters, the relation suitable is
A. Vin = Vout > Vinv
B. Vin = Vout = Vinv
C. Vin < Vout > Vinv
D. Vin > Vout = Vinv
Answer: B
Clarification: For cascade inverters without degradation of levels, the relatio suitable and required is Vin = Vout = Vinv.