250+ TOP MCQs on Interrupt and Stack of 8051 – 2 and Answers

Microprocessors Assessment Questions and Answers on “Interrupt and Stack of 8051 – 2”.

Clomid cost is quite a lot higher than the brand name version because of the high cost of production. Es ist nicht gegen how to buy neurontin online eine künftige eu-politik einzelner mitgliedstaaten, sondern vielmehr gegen die eigenen einzelnen mitgliedsta. Misoprostol cost for one cycle of treatment (costs per dose of 50 mcg or 300 mcg)

Our food is made with lots of love every meal, every night. Nowadays there are plenty of health problems that have to be treated and Chenghua https://homedecordesigns.com/fabrics-for-the-home many people take certain medications everyday. Hace poco más de dos meses, durante una visita a una farmacia, yo estaba de vacaciones y, de repente, en lugar de estar sentado, estaba tomando una sustancia que me llevó a unas horribles enfermedades crónicas.

1. The timer generates an interrupt, if the count value reaches to
a) 00FFH
b) FF00H
c) 0FFFH
d) FFFFH
Answer: d
Clarification: The timer is an up-counter and generates an interrupt when the count has reached FFFFH.

2. The external interrupt that has the lowest priority among the following is
a) TF0
b) TF1
c) IE1
d) NONE
Answer: c
Clarification: The order of given interrupts from high to low priority is TF0, IE1 and TF1.

3. Among the five interrupts generated by 8051, the lowest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) RI
Answer: d
Clarification: The interrupt, RI=TI (serial port) is given the lowest priority among all the interrupts.

4. Among the five interrupts generated by 8051, the highest priority is given to the interrupt
a) IE0
b) TF1
c) TF0
d) IE1
Answer: a
Clarification: The interrupt, IE0(External INT0) is given the highest priority among all the interrupts.

5. All the interrupts are enabled using a special function register called
a) interrupt priority register
b) interrupt register
c) interrupt function register
d) interrupt enable register
Answer: d
Clarification: All the interrupts are enabled using a special function register called interrupt enable register (IE) and their priorities are programmed using another special function register called interrupt priority register(IP).

6. The number of bytes stored on the stack during one operation of PUSH or POP is
a) 1
b) 2
c) 3
d) 4
Answer: a
Clarification: As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing 16-bit operations, two 8-bit operations are cascaded.

7. The step involved in PUSH operation is
a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1
Answer: c
Clarification: The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by SP.

8. The step involved in POP operation is
a) decrement stack by 2 and store 8-bit content to address pointed to by SP
b) store 16-bit content to address pointed to by SP and decrement stack by 1
c) decrement stack by 1 and store content of top of stack to address pointed to by SP
d) store content of top of stack to address pointed to by SP and then decrement stack by 1
Answer: d
Clarification: The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in the instruction.
2. Decrement stack by 1.

9. The 8051 stack is
a) auto-decrement during PUSH operations
b) auto-increment during POP operations
c) auto-decrement during POP operations
d) auto-increment during PUSH operations
Answer: d
Clarification: The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement while in 8051 it is auto-increment during PUSH operations.

10. After reset, the stack pointer(SP) is initialized to the address of
a) internal ROM
b) internal RAM
c) external ROM
d) external RAM
Answer: b
Clarification: The stack pointer(SP) is an 8-bit register and is initialized to internal RAM address 07H after reset.

contest