Basic IOT Questions on “Microcontroller (ARM 7- Pipelining)”.
1. What are the pipelining stages include?
a) Fetch, Decode, Write
b) Fetch, Decode, Execute
c) Fetch, Execute, Write
d) Fetch, Decode, Execute, Write
Answer: a
Clarification: ARM7 core has 3-stage pipeline that increases instruction flow through processor up to three times. So each instruction is executed in 3 stages:
Fetch – instruction is fetched from memory and placed in pipeline
Decode – instruction is fetched and data-path signals prepared for next cycle
Execute – instruction from prepared data-path reads from registry bank, shifts operand to ALU and writes generated result to dominant register.
2. What is pipe lining?
a) Non linear
b) Linear
c) Linear and Non linear
d) Sometimes both
Answer: b
Clarification: Pipeline is linear, which means that in simple data processing processor executes one instruction in single clock cycle which while individual instruction takes three clock cycles.
3. What are the no of pins that are in the ARM7 processors?
a) 65 pin with QFP
b) 45 Pin with QFP
c) 45 pin with LLC
d) 65 pin with DIP
Answer: d
Clarification: The ARM7 family members have different packages, such as DIP(Dual In Line), QFP(Quad Flap Package), LLC(Leadless Chip Carrier) they all have 40 pins that are dedicated to different functions. Especially 8051 has a Quad Flap Package.
4. Using what the processor wake-up from power-down?
a) External Interrupts
b) Internal interrupts
c) Serial Programming
d) Program Counter
Answer: a
Clarification: The AVR7 processor wakes up from power down mode via external interrupt or BOD.
5. What is the flash memory for LPC2141?
a) 34kB
b) 32kB
c) 128kB
d) 256kB
Answer: b
Clarification: It is the first series of ARM7. This memory is used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It can also be programmed in system via serial port.
6. What are the categories in the vectored interrupt controller?
a) Fast interrupt request
b) Non vectored interrupt request
c) Non-vectored IQR
d) Fast interrupt request, Non vectored interrupt request and Non-vectored IQR
Answer: d
Clarification: The vectored Interrupt controller accepts all the interrupts request inputs and categorizes them as Fast Interrupt Request, Vectored Interrupt Request, and Non Vectored IQR as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
7. Each peripheral has an interrupt line?
a) True
b) False
Answer: a
Clarification: Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
8. What is pin connect block?
a) All pins are having a function without reserved
b) Some pins are Reserved
c) Pins have more than one function
d) Multiplexing of some pins
Answer: c
Clarification: The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.
9. What is the size of ADC and DAC?
a) 16 bit
b) 10 bit
c) 8 bit
d) 32 bit
Answer: b
Clarification: The converters are single 10-bit successive approximation analog to digital converters. While ADC0 has 6 channels, ADC1 has 8 channels. And DAC output voltage is the vref voltage.
10. How many processors are used in the Instruction pipelining?
a) One
b) Two
c) Three
d) Four
Answer: a
Clarification: Pipelining is a technique for implementing instruction level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instructions, by dividing incoming instructions into the series of sequential steps.
11. Which signal is used for pipelining on bis cycle in ARM710T?
a) BWAIT
b) BTRAN
c) BLOK
d) BCLK
Answer: b
Clarification: The signal BTAN[1:0] is placed by one bus cycle. This pipelining should be taken into account when these signals are being decoded. The value of BTRAN[1:0] indicates whether the next bus cycle is a data cycle or an address cycle.
12. _______ pin can be used to extend memory access in whole cycle increments.
a) BTRAN
b) BLOK
c) BWAIT
d) BCLK
Answer: c
Clarification: BWAIT pin can be used to extend memory access in whole cycle increments. BWAIT is driven by the selected slave during the low phase of BCLK.
13. How many DC-DC converters interfaces in ARM7100?
a) 5
b) 3
c) 4
d) 2
Answer: d
Clarification: ARM7100 has two programmable duty ratio 96KHz clock output which is intended to be used as drivers for DC to DC converter in the PSU subsystems.
14. The ARM7TDMI-S uses which pipelining?
a) 2-Stage
b) 3-Stage
c) 4-Stage
d) 5-Stage
Answer: b
Clarification: A 3-stage pipelining is used, so instructions are executed in three stages: Fetch, Decode, Execute.
15. The ARM7TDMI-S processor has __________ types of memory cycle.
a) 5
b) 3
c) 4
d) 2
Answer: c
Clarification: The ARM7TDMI-S processor has 4 types of memory cycle: Non sequential cycle, Sequential cycle, cp processor register transfer cycle, internal cycle.