250+ TOP MCQs on Optimization of Inverters-1 and Answers

VLSI Multiple Choice Questions on “Optimization of Inverters-1”.

1. Reduction in power dissipation can be brought by
A. increasing transistor area
B. decreasing transistor area
C. increasing transistor feature size
D. decreasing transistor feature size
Answer: A
Clarification: The 3:1 reduction in power dissipation can be brought at the expense of increasing the transistor area by 50%.

2. When does the longest delay occur in 8:1 inverters?
A. during 1 to 0 transition
B. during 0 to 1 transition
C. during faster speed
D. delays are always short
Answer: B
Clarification: In 8:1 inverters, the longest delay will occur when the output of the first stage is changing from logic 0 to 1 and capacitance must charge through pull-up resistance.

3. In inverter during logic 1 to 0 transition, capacitance discharges at
A. pull-up resistance
B. pull-down resistance
C. both pull-up and pull-down
D. at gate
Answer: B
Clarification: During the logic 1 to 0 transition, the capacitance which is charged through pull-up must always discharge through pull-down transistor at first stage.

4. In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as
A. 5Ʈ
B. 20Ʈ
C. 40Ʈ
D. 50Ʈ
Answer: C
Clarification: For minimum pull-down feature size nMOS 8:1 inverter, the logic 0 to 1 transition delay can be given as 8Rs x 5 square Cg which gives 40Ʈ.

5. In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as
A. 5Ʈ
B. 20Ʈ
C. 40Ʈ
D. 50Ʈ
Answer: A
Clarification: 8:1 nMOS inverter allows stray and wiring capacitance and the logic 1 to 0 transition delay can be given as 1Rs x 5 square Cg which gives 5Ʈ.

6. For a regular 8:1 inverter, the transition delay is given as
A. 10Ʈ
B. 20Ʈ
C. 21Ʈ
D. 25Ʈ
Answer: C
Clarification: For 8:1 inverter the logic 0 to 1 transition delay can be given as 21Ʈ and logic 1 to 0 transition delay can be given as 2(1/3)Ʈ.

7. The area of CMOS inverter is proportional to
A. area of n device
B. area of p device
C. total area of n and p device
D. square of minimum feature size
Answer: C
Clarification: The area of a basic CMOS inverter is proportional to the total area occupied bu the p and n devices (WpLp + WnLn).

8. The ratio of Wp/Wn can be given as
A. 1:2
B. 2:1
C. 1:1
D. 2:2
Answer: C
Clarification: Minimum area can be achieved by choosing minimum dimensions for Wp, Wn, Lp, Ln which is 2λ and the ratio of Wp/Wn can be given as 1:1.

9. Switching power dissipation can be given as
A. Cl x Vdd x f
B. Vdd² x f
C. Cl x Vdd²
D. Cl x Vdd² x f
Answer: D
Clarification: Switching power dissipation Psd can be given as Cl x Vdd² x f where Cl is load capacitance, Vdd is power supply voltage and f is the frequency of switching.

10. Load capacitance can be minimized by
A. increasing A
B. decreasing A
C. increasing Psd
D. does not depend on A
Answer: B
Clarification: For fixed Vdd and f, minimizing Psd requires minimizing Cl which can be minimized by decreasing area A as it is directly proportional to gate area.

11. Rise time and fall time can be equalized by
A. βn = βp
B. βn = 2βp
C. βp = 2βn
D. βn = 1/2βp